| Age | Commit message (Collapse) | Author | Files | Lines |
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These two exceptional cases were rarely observed in a slave device
reset or in a peer master reset conditions.
1. aspeed-i2c-bus 1e78a480.i2c-bus: irq handled != irq. expected 0x00000030, but was 0x00000020
when master goes from ASPEED_I2C_MASTER_STOP to
ASPEED_I2C_MASTER_INACTIVE state due to an
ASPEED_I2CD_INTR_ABNORMAL event. In this case,
ASPEED_I2CD_INTR_NORMAL_STOP should be simply ignored without
printing out the error message.
2. aspeed-i2c-bus 1e78a480.i2c-bus: irq handled != irq. expected 0x00000010, but was 0x00000000
when master already went to ASPEED_I2C_MASTER_INACTIVE. H/W sends
one additional ASPEED_I2CD_INTR_NORMAL_STOP event but it's a
garbage because driver is already in inactive state so filter it
off from the error message printing out.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Change-Id: I94794a9612a7e8db445591e490bad6adae0faacf
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Fixup an unexpected bus holding case caused by a message sending
failure on packet which has a holding message. In case of an error
on sending a message, a bus holding should be immediately released
by itself to prevent a race condition because user space doesn't
send an unhold message when a packet which has hold message fails.
This case was obversed in PLDM stress test which can make intensive
AIC resets so driver was in a severe condition that has lots of
arbitration losses and abnormal stops.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Change-Id: Ibd169c791d0c24f41932ea676d4e187ddbd3e140
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If we're only using CPU number as MFD cell id, we don't have a way to
avoid a collision in case we have multiple adapters able to communicate
with the same CPUs.
[ 794.916872] sysfs: cannot create duplicate filename '/bus/platform/devices/peci-cputemp.0'
[ 795.452507] intel_peci_client 1-30: Failed to register child devices: -17
[ 795.460238] intel_peci_client: probe of 1-30 failed with error -17
To fix this problem, let's use both adapter number and cpu number to
calculate MFD cell id.
Change-Id: If0559a0b629081e6201b4ce93cb8bc649dd2a258
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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To avoid conflicts with other JTAG hardware probes such as XDP, ASD
must disable JTAG Master controller output when ASD connection is not
in use.
This commit fixes the output disable for AST26xx series which needs
ASPEED_JTAG_CTRL and ASPEED_JTAG_GBLCTRL to be cleared for all SW,
HW1 and HW2 modes.
Test:
1. Run jtag_test
2. Run ASD Sanity(using XDP) - Failed here before
3. Run jtag_test
4. Run ASD Sanity(using ASD)
5. Run ASD Sanity(using XDP) - Failed here before
6. ASD Sanity(using ASD)
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Change-Id: I4f403f4b8412ab96cee195412cc412360845b6d0
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This patch makes time window setting to be cleared when disabling
power capping just like others settings.
Change-Id: I3a5fc9c1eb6a5787d131bf69cc18a5dae94a99f0
Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
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This patch makes timestaps catching to happen just after PECI
transaction. It makes reading more accurate since PECI request can hang
while waiting in PECI driver queue.
Change-Id: I1a356caa59148a5cebcfcdf89211038bfadb40d3
Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
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This commit adds an interface for reading chip unique id value.
Optionally, the id can be encrypted using a dts-supplied hash data.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
Change-Id: Ifd98500ea87b3d40e1738e583e077a74851fae35
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When we program TX command register, it requires packet data size in
dwords. Since the aspeed-mctp driver doesn't implement MCTP protocol, it
copies MCTP packet "as it" form userspace and uses size from write()
syscall to program TX command.
If the size from write() doesn't match the payload length in packet PCIe
VDM header, it causes MCTP HW to stop working and we are not able to
reset it without platform power cycle.
To avoid HW issues, let's verify if the data size from write() matches
the payload length in PCIe VDM header.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Change-Id: I6da14babadcc65cb2ba4a2b685495d1baa92c169
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This change adds the SPI region needed for AFM(Attestation
Firmware Manifest) which is used by SPDM Requester in PFR RoT.
The change realigns the remaining flash region and
appends the 256KB AFM region to staging region and reserves
768KB region for PSU and HSBP firmware.
Tested: BMC boot in non-PFR and PFR environment.
Change-Id: I322eebbdbb5dcffbfc45b8b50650ba4aaa5af186
Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com>
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This commit adds a raw value setting interface for uart routing
to provide an atomic way of switching the route.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Change-Id: Id8b80f44f9a503d9f25a692211fc5ec78500ce68
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To support communication with NVDIMM controllers, add definitions for
these I3C devices. Each bus now has two definitions for each DIMM slot.
If populated with a DDR5 DIMM, the SPD Hub device will be used to gather
temperature readings. If populated with an NVDIMM, we'll only need to
talk to the controller sitting behind the hub (local device type 1011b),
to read temperature and use the FW mailbox.
This also removes some logic in the I3C driver which restricts use of
certain addresses due to signal integrity paranoia. An NVDIMM controller
in slot 6 of any bus is blocked by this logic, and unfortunately we
don't have any control over the static address scheme used on the SPD
bus, so the restriction must be removed.
Tested:
Probed I3C busses successfully with DIMMs installed in busses 0 and 1:
$ gpioset $(gpiofind FM_SPD_SWITCH_CTRL_N)=1
$ echo 1e7a2000.i3c0 > /sys/bus/platform/drivers/dw-i3c-master/bind
$ echo 1e7a3000.i3c1 > /sys/bus/platform/drivers/dw-i3c-master/bind
$ ls /dev/i3c*
/dev/i3c-0-3c000000000 /dev/i3c-0-3c000000001 /dev/i3c-0-3c000000002
/dev/i3c-0-3c000000003 /dev/i3c-0-3c000000004 /dev/i3c-0-3c000000005
/dev/i3c-0-3c000000006 /dev/i3c-0-3c000000007 /dev/i3c-0-3c000000008
/dev/i3c-0-3c000000009 /dev/i3c-0-3c00000000a /dev/i3c-0-3c00000000b
/dev/i3c-0-3c00000000c /dev/i3c-0-3c00000000d /dev/i3c-0-3c00000000e
/dev/i3c-1-3c000000000 /dev/i3c-1-3c000000001 /dev/i3c-1-3c000000002
/dev/i3c-1-3c000000003 /dev/i3c-1-3c000000004 /dev/i3c-1-3c000000005
/dev/i3c-1-3c000000006 /dev/i3c-1-3c000000007 /dev/i3c-1-3c000000008
/dev/i3c-1-3c000000009 /dev/i3c-1-3c00000000a /dev/i3c-1-3c00000000b
/dev/i3c-1-3c00000000c /dev/i3c-1-3c00000000d /dev/i3c-1-3c00000000e
Change-Id: I016450edad1ed4ec981500f04122976f1647b8ee
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
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The size of mailbox differ from AST2500, AST2600 A0 and A1. Add an ioctl
support to fetch the mailbox size.
Tested:
Verfied ioctl call returns mailbox size as expected.
Change-Id: I4e261aaf8aa3fb108d6ad152d30a17b114d70ccd
Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
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Using an overshift test environment where we execute a continuous
JTAG R/W operation during hours we discover that in one of million
ocurences for AST26xx TDO read occurred before JTAG Master controller
reflected real tdo value on ASPEED_JTAG_SW.
It was needed to add two delays during the SW xfer process to
prevent this issue. We tested several delay options and found that
using a read/write to ASPEED_JTAG_PADCTRL1(not used in SW mode)
register gives the JTAG Master controller enough time to process
the xfer with the lowest performance impact among the delay options.
For AST25xx an extra delay was not required.
Test:
All of the following in SW mode:
AST26xx(SPR) ASD Sanity finished successfully.
AST26xx(SPR) Overshift test with 4K iterations finished successfully.
AST26xx(SPR) jtag_test with 8M iterations finished successfully.
AST25xx(ICX) ASD Sanity finished successfully
AST25xx(ICX) jtag_test with 8M iterations finished successfully.
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Change-Id: Idf82632a564495e0a69075c9b842e84d39419612
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This commit adds silicon_id sub-node into misc_control node.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Change-Id: I60c09b654ca8a8881e5df4be07f062280210e570
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Modified the Aspeed global driver as a platform driver instead of a
postcore initialized one to make it get a reset control resource
properly while probing the module. To make it probed ahead of bus
modules, it also modifies the object order in makefile.
Change-Id: Icefb06c1a4548417aa09f53da5cb2f61ba6f8d09
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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- Move TDI state matrix to core header file
- These changes are done based on feedback from Paul
Fertser, from the OpenOCD.
Test:
SPR ASD Sanity and jtag_test finished successfully.
ICX ASD Sanity and jtag_test finished successfully.
Change-Id: Idb612e50d5a8ea5929f7c9241d279c345587983a
Signed-off-by: Castro, Omar Eduardo <omar.eduardo.castro@intel.com>
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JTAG xfer length is measured in bits and it is allowed to send non 8-bit
aligned xfers. For such xfers we will read the content of the remaining
bits in the last byte of tdi buffer and restore those bits along with
the xfer readback.
Add also linux types to JTAG header to remove external dependencies.
Test:
SPR ASD Sanity and jtag_test finished successfully.
SKX ASD Sanity and jtag_test finished successfully.
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
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Intel doesn't use transmit clock output of RMII4 module so this
commit customize RMII4 pin ctrl group by removing the F24 pin
setting from RMII4.
This is a downstream customization. Do not upstream it.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Add cleanup fixes after implementing energy sensor for all
modules: cpu, dimm, platform to make all files consistent.
Signed-off-by: Olender, Agata <agata.olender@intel.com>
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Create a low level function to handle xfer interrupts and map
corresponding interrupt functions for AST25xx and AST26xx in
HW1 and HW2 xfer modes.
By default JTAG driver still uses polling. Interrupt support
needs to be enabled with USE_INTERRUPTS macro.
Remove also unused SCU reference.
Test:
AST26xx(SPR) ASD Sanity and jtag_test using HW2 polling.
AST26xx(SPR) ASD Sanity and jtag_test using HW1 polling.
AST26xx(SPR) ASD Sanity and jtag_test using HW2 interrupt.
AST26xx(SPR) ASD Sanity and jtag_test using HW1 interrupt.
AST26xx(SPR) jtag_test using SW mode.
AST25xx(SKX) ASD Sanity and jtag_test using HW polling.
AST25xx(SKX) ASD Sanity and jtag_test using HW interrupt.
AST25xx(SKX) jtag_test using SW mode.
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
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This commit is about disabling reading DRAM_MIN_PWR from
DRAM_POWER_INFO PCS. Starting from SPR DRAM_MIN_PWR is deprecated. BIOS
does not update DRAM min power anymore.
Value of 0 shall be reported as DRAM min power.
Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
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This commit replaces 'Maximal DRAM Power' (MSR@61Ch -
MSR_DRAM_POWER_INFO_HIGH) with the 'Spec DRAM Power'('TDP') (MSR@61Ch -
MSR_DRAM_POWER_INFO_LOW) while maximal DRAM power calculation. This is
to be compliant with SPS ME Node Manager. In case package power it
already works with the same way - TDP is taken as maximal power.
Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
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This commit adds CPU generation info for ICX-D Xeon family.
Signed-off-by: Saravanan Palanisamy <saravanan.palanisamy@intel.com>
Signed-off-by: Anoop S <anoopx.s@intel.com>
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This commit adds CPU generation info for ICX family.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit adds pwm chip driver support into aspeed-g6-pwm-tacho
driver to enable beep speaker driver. The pwm chip driver cannot
be added as a separate platform driver because it makes resource
conflicts with existing pwm-tacho driver so it uses hacky tweak
on the existing driver.
Note: Do not try upstream this hacky implementation.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Change-Id: I22ad12be2ae3a061d7942fec813cdb11be321db7
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Add support for energy consumption of DIMMs sensor.
Energy is reported in micro Joules and exposed under
energyN_input file.
Signed-off-by: Olender, Agata <agata.olender@intel.com>
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The ASPEED BMC SoCs have many knobs and switches that are sometimes
design-specific and often defy any approach to unify them under an
existing subsystem.
Add a driver to translate a devicetree table into sysfs entries to
expose bits and fields for manipulation from userspace. This encompasses
concepts from scratch registers to boolean conditions to enable or
disable host interface features.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Change energy sensor to cumulative energy sensor.
Actually energy sensor implementation works as simply translation for
value read from PCS register to microjoules.
With this change, energy sensor will behave as accumulative sensor>
After every read on energyN_input file new energy sample will be
gathered, and the difference between new sample and previous one will
be added to sensor value.
This approach solves problems with counters overflow and interpretation
of the energy sensor value.
Signed-off-by: Olender, Agata <agata.olender@intel.com>
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Remove modparam to enable peci-mctp probe and enable it by default.
Tested: Verified that peci-mctp driver probes correctly:
peci peci-1: cdev of adapter [peci-mctp] registered as minor 1
Manually verified that applications using PECI work correctly.
Signed-off-by: Karol Wachowski <karol.wachowski@intel.com>
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When peci-mctp finds that there is no discovered CPU, it queries
aspeed-mctp to read BDFs for each static EID reserved by CPU socket.
If BDF is non-zero, peci-mctp reads CPUNODEID_CFG register to determine
CPU represented by this endpoint.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Right now, send and receive API functions are called directly from xfer
handler. Let's add a dedicated helper function responsible for
send/receive to allow issuing PECI messages originated in peci-mctp
driver.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Recently, aspeed-mctp driver functionality was extended to store BDF
values for already discovered MCTP endpoints on PCIe bus.
Let's expose kernel API to read BDF based on endpoint ID.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Support interrupt generation for both 16 and 32 mailbox registers.
Tested:
After applied this patch, write the mailbox registers from BIOS side,
the misc manager can capture the new mailbox data.
Signed-off-by: Yong Li <yong.b.li@linux.intel.com>
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Adjust energy sensor to be 31 bits counter and return only positive
values using S32 type - that is a part of common sensor struct for
all hwmon peci sensors.
Signed-off-by: Olender, Agata <agata.olender@intel.com>
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Fixed out of range write by ignoring usage of CCC_WORKAROUND
when DEVICE_ADDR_TABLE_POINTER register returns 0 value. It
allows to use simulation software like QEMU where I3C may not
be implemented and all its registers are set to zeros.
Signed-off-by: Wludzik, Jozef <jozef.wludzik@intel.com>
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This commit moves Aspeed eSPI driver from misc to soc/aspeed tree
to make correct probing order for LPC and eSPI driver. Since LPC
runs over eSPI, eSPI driver should be registered ahead of LPC
driver.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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AST2600 A1 has separate reset control for LPC and eSPI so this
commit fix the index definition to make it work on AST2600 A1.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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There is a data to send/read FIFO used by the AST26xx series JTAG Master
Controller when hardware mode 1 and 2 transfer is selected. The proper
usage of this FIFO allows AST26xx JTAG peripheral to xfer up to 512 bit
without CPU interaction.
In this commit we included a delay after FIFO R/W operations to provide
enough time for JTAG master controller to handle FIFO transitions.
Additionally we included aspeed_jtag_xfer_hw_26xx() to separate AST25xx
and AST26xx HW1 xfer handlers and setup the delay only for AST26xx
series.
These changes doesn't affect Software mode or AST25xx functionality.
Tested:
ASD Sanity works finished successfully for AST26xx in SW/HW1/HW2 modes
50 times jtag_test -h -t 8 -i 8000000 (HW2)
50 times jtag_test -h -t 8 -i 8000000 (HW1)
50 times jtag_test -i 8000000 (SW)
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
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Now that it is possible to send PECI frames via aspeed-mctp driver,
let's add aspeed-peci-mctp node to allow bind peci-mctp-aspeed adapter
driver.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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PECI frames can be encapsulated into MCTP PCIe VDM packets.
Let's add driver that allows to send PECI frames via aspeed-mctp driver.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Currently driver submits 1 (or rarely more than 1) packet then
waits until HW signals transmission completion before sending
more packets. This logic requires interrupt after each packet,
aspeed_mctp_tx_tasklet() is invoked twice per packet.
New logic uses TX ring correctly, packets are added to the end of
circular ring buffer. The driver does not have to wait for HW to
complete transmission of enqueued packets before adding more packets
to TX queue. Interrupt is generated only if TX ring if full.
This change significantly improves packet transmission performance:
PECI GetTemp command takes ~25us instead of ~30us.
This change also fixes sporadic TX hangs during host reboot seen
with current driver.
Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com>
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If self EID is known then the driver updates source EID in
MCTP header of sent packets. For MCTP control packets the
source EID is not updated as it may disrupt MCTP discovery flow.
Self EID is determined from list of known endpoints provided
by ASPEED_MCTP_IOCTL_SET_EID_INFO IOCTL.
Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com>
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This commit ports I3C updates from Aspeed SDK v00.06.00.
Note: Should be refined to get upstreamed.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
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Add support for energy consumption of CPU package sensor.
Energy is reported in micro Joules and exposed under
energyN_input file.
Signed-off-by: Olender, Agata <agata.olender@intel.com>
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Under even moderate traffic the driver can miss a lot of received
packets and eventually stops receiving packets at all.
There is an bug in AST2600 RX logic where HW does not wrap
around RX read buffer pointer correctly. Current driver
workaround for this bug resets RX HW read pointer to 0 whenever
it reaches end of the RX buffer ring - this does not work properly
if more than 1 packet is received while RX pointer is close to
the end of the RX buffer ring - in such case HW can detect ring
full condition and stop RX.
The new workaround has different logic: it sets HW buffer count to
4n - 1 and updates driver maintained RX write pointer so it
tracks HW read pointer to prevent hardware from stopping.
Received packets are located by looking into RX data buffers
rather that HW read pointer that contains incorrect value anyway.
Driver never resets HW read pointer, HW is receiving packets without
any interference form the driver.
Also handle RX_CMD_NO_MORE_INT - if RX ring if full then
HW will clear RX_CMD_READY bit and we need to re-enable it
once we free some space in RX ring.
Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com>
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Initial value of I2CD18 is undefined according to the datasheet
so this commit adds the I2CD18 register clearing code into bus
initialization function to prevent any unexpected slave match
events.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
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Right now, PECI revision is determined using a result of GetDIB() PECI
command. Because GetDIB() may not be supported by all type of physical
media that provides PECI, we need an alternative.
Until we figure how to determine PECI revision there (if we can't do
that, we'll fallback to device tree), let's allow to hardcode PECI
revision as a property of hardware adapter.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Some protocols that are already implemented in kernel can be
encapsulated in MCTP packets. To allow use aspeed-mctp internally in
kernel space, let's allow to use selected functions outside of
aspeed-mctp.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Right now, TX ring contains packets with PCIe header already swapped
to little endian (byte order expected by HW), while RX ring contains
packets with PCIe header already swapped to network order (expected by
userspace).
Let's keep TX packets in network order and swap before write to HW
buffer.
To make it more readable, let's extract swapping into a helper function.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Implement two new ioctls for storing EID related information:
* ASPEED_MCTP_IOCTL_GET_EID_INFO
* ASPEED_MCTP_IOCTL_SET_EID_INFO
Driver stores EID mapping in a list which is traversed when
one tries to get information using ASPEED_MCTP_IOCTL_GET_EID_INFO
ioctl, when given EID mapping is not found in the list, next entry
is returned. When there are no entries with EIDs higher than specified
in the IOCTL call -ENODEV is returned.
Whenever new information about EID mapping is stored with
ASPEED_MCTP_IOCTL_SET_EID_INFO ioctl driver empties exsiting
list of mappings and creates new one based on user input.
After insertion list is sorted by EID. Invalid input
such as duplicated EIDs will cause driver to return -EINVAL.
Signed-off-by: Karol Wachowski <karol.wachowski@intel.com>
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