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The IBI_WIP code is not used and not expected to be used in the future.
Remove it.
Change-Id: I6a3808c3808ab827c3ac326dbf1be244beffd6f6
Signed-off-by: Oleksandr Shulzhenko <oleksandr.shulzhenko.viktorovych@intel.com>
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CPU can return invalid temperature readings prior to BIOS-PCU
handshake RST_CPL3 or RST_CPL4 completion so add a fix to filter
the invalid readings out.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
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This commit adds 'aspeed,int-vref-microvolt' and
'aspeed,battery-sensing' properties into ADC nodes for Intel
AST2600 BMC platforms.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit adds rtc-pch node into aspeed-bmc-intel-ast2500 and
aspeed-bmc-intel-ast2600 to enable PCH RTC driver.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
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This commit adds debug printing out to check caller PID for traffic
profiling.
The printing can be enabled by this command:
echo -n 'file drivers/peci/peci-core.c line 218 +p' > /sys/kernel/debug/dynamic_debug/control
echo '8' > /proc/sys/kernel/printk
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit fixes a build break which is caused by an incompatible
compare function parameter of list_sort() call.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
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Before this change JTAG HW2 mode shift operation failed to process a
shift request when current state was Exit IR/DR for the same type of
xfer SHIFTIR/SHIFTDR respectively. After this change we will
support shift operations in HW2 mode from the following jtag states:
For SHIFTDR: JTAG_STATE_SHIFTDR, JTAG_STATE_IDLE, JTAG_STATE_TLRESET,
JTAG_STATE_PAUSEDR, JTAG_STATE_EXIT1DR and
JTAG_STATE_EXIT1IR
For SHIFTIR: JTAG_STATE_SHIFTIR, JTAG_STATE_IDLE, JTAG_STATE_TLRESET,
JTAG_STATE_PAUSEIR, JTAG_STATE_EXIT1IR and
JTAG_STATE_EXIT1DR
Test:
ASD Sanity(SW mode) finished successfully(SPR)
ASD Sanity(HW mode) finished successfully(SPR)
Cscripts(SW mode) finished successfully(SPR)
Cscripts(HW mode) finished successfully(SPR)
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Change-Id: Ide878b8986639c63e41c2bc360e06a261cdffee5
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The current hwirq is calculated based on the old GPIO pin order(input
GPIO range is from 0 to ngpios - 1).
It should be calculated based on the current GPIO input pin order(input
GPIOs are 0, 2, 4, ..., (ngpios - 1) * 2).
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
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Add an else-if condition in the probe function to check whether ngpios is
multiple of 8.
Per AST datasheet, numbers of available serial GPIO pins in Serial GPIO
Configuration Register must be n bytes. For instance, if n = 1, it means
AST SoC supports 8 GPIO pins.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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Replace all of_property_read_u32() with device_property_read_u32().
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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The current design initializes irq->chip from a global irqchip struct,
which causes multiple sgpio devices use the same irq_chip.
The patch moves irq_chip to aspeed_sgpio struct for initializing
irq_chip from their private gpio struct.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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AST SoC supports *retain pin state* function when wdt reset.
The patch adds set_config function for handling sgpio reset tolerance
register.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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The maximum number of gpio pins of SoC is hardcoded as 80 and the gpio pin
count mask for GPIO Configuration register is hardcode as GENMASK(9,6).
However, AST2600 has 2 sgpio master interfaces, one of them supports up
to 128 gpio pins and pin count mask of GPIO Configuration Register is 5
bits.
The patch adds ast2600 compatibles, removes MAX_NR_HW_SGPIO and
corresponding design to make the gpio input/output pin base are determined
by ngpios.
The patch also removed hardcoded pin mask and adds ast2400, ast2500,
ast2600 platform data that include gpio pin count mask for GPIO
Configuration Register.
The original pin order is as follows:
(suppose MAX_NR_HW_SGPIO is 80 and ngpios is 10 as well)
Input:
0 1 2 3 ... 9
Output:
80 81 82 ... 89
The new pin order is as follows:
Input:
0 2 4 6 ... 18
Output:
1 3 5 7 ... 19
SGPIO pin id and input/output pin mapping is as follows:
SGPIO0(0,1), SGPIO1(2,3), ..., SGPIO79(158,159)
For example:
Access SGPIO5(10,11)
Get SGPIO pin 5 (suppose sgpio chip id is 2)
gpioget 2 10
Set SGPIO pin 5 (suppose sgpio chip id is 2)
gpioset 2 11=1
gpioset 2 11=0
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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Currently, after TX channel wr_ptr reaches the maximum value, there is
no mechanism to clear it. The driver expects that the HW will make
forward progress, and eventually the buffer will have free space
available. That's not true for some reset scenarios and when this
happens, we may end up with a blocked full channel.
While we could fix it by just adding a trigger after reset, this may
cause userspace to receive unexpected responses for packets that got
stuck in queues during reset.
Let's fix it by flushing both TX channel and client rings.
Note: The barriers are necessary just to enforce ordering between flush
and producing new packets by the clients (we don't want to flush packets
that were sent after reset, just the ones that were sent before it) but
to keep things consistent, introduce helpers for all priv->pcie.bdf
accesses.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Change-Id: I457a05a6e7f0cb1fd8ce6f2bff6a59b166d32149
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Previous this change we send JTAG state machine to RTI in all shifts
that end state was EXIT1IR/EXIT1DR. With this rule we were able to
guarantee a smooth chain transition in HW mode (chain is expected to
be in RTI after chain has been selected). However, there were
uncovered cases such as Go to Ex1IR and then Go to ShfDR which
doesn't expect to visit RTI.
With this change AST26xx shift behavior in HW mode will be more
accurate to what it is being requested. JTAG state machine will
remain in EXIT1IR/EXIT1DR when those end states are being sent to
the aspeed_jtag_xfer_hw2 driver function.
It is now expected that ASD application calculates the right end
state and send either EXIT1IR, EXIT1DR, RTI or PAUSEDR to control
shift operations and JTAG state transitions in HW mode.
Additionally aspeed_jtag_set_tap_state_hw2() function was updated to
handle go to RTI from EXIT1 included in two different network
packets.
Tested:
Using Software, HW1 and HW2 modes:
ASD Sanity ended successfully.
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Change-Id: Ic49b0ce26c49d08e806c29e5ae72a4b3b7e68553
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update the correct offset value of sio_status register to 0x10C.
Tested:
sio_status register updated after core bios done signal sent from BIOS.
before: cat /sys/devices/platform/ahb/ahb:apb/1e789000.lpc/1e789000.lpc:
regs/sio_status
16
after: cat /sys/devices/platform/ahb/ahb:apb/1e789000.lpc/1e789000.lpc:
regs/sio_status
17
before: devmem 0x1e78910c
0x00000100
after: devmem 0x1e78910c
0x00000111
Signed-off-by: Chalapathi Venkataramashetty <chalapathix.venkataramashetty@intel.com>
Change-Id: I6849980649f3fe353d67e1d131163a6aed777d77
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Add SMI event triggering support.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Change-Id: I711b5642a654e671a2d97d3079e3a1a055d400a0
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These two exceptional cases were rarely observed in a slave device
reset or in a peer master reset conditions.
1. aspeed-i2c-bus 1e78a480.i2c-bus: irq handled != irq. expected 0x00000030, but was 0x00000020
when master goes from ASPEED_I2C_MASTER_STOP to
ASPEED_I2C_MASTER_INACTIVE state due to an
ASPEED_I2CD_INTR_ABNORMAL event. In this case,
ASPEED_I2CD_INTR_NORMAL_STOP should be simply ignored without
printing out the error message.
2. aspeed-i2c-bus 1e78a480.i2c-bus: irq handled != irq. expected 0x00000010, but was 0x00000000
when master already went to ASPEED_I2C_MASTER_INACTIVE. H/W sends
one additional ASPEED_I2CD_INTR_NORMAL_STOP event but it's a
garbage because driver is already in inactive state so filter it
off from the error message printing out.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Change-Id: I94794a9612a7e8db445591e490bad6adae0faacf
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If we're only using CPU number as MFD cell id, we don't have a way to
avoid a collision in case we have multiple adapters able to communicate
with the same CPUs.
[ 794.916872] sysfs: cannot create duplicate filename '/bus/platform/devices/peci-cputemp.0'
[ 795.452507] intel_peci_client 1-30: Failed to register child devices: -17
[ 795.460238] intel_peci_client: probe of 1-30 failed with error -17
To fix this problem, let's use both adapter number and cpu number to
calculate MFD cell id.
Change-Id: If0559a0b629081e6201b4ce93cb8bc649dd2a258
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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To avoid conflicts with other JTAG hardware probes such as XDP, ASD
must disable JTAG Master controller output when ASD connection is not
in use.
This commit fixes the output disable for AST26xx series which needs
ASPEED_JTAG_CTRL and ASPEED_JTAG_GBLCTRL to be cleared for all SW,
HW1 and HW2 modes.
Test:
1. Run jtag_test
2. Run ASD Sanity(using XDP) - Failed here before
3. Run jtag_test
4. Run ASD Sanity(using ASD)
5. Run ASD Sanity(using XDP) - Failed here before
6. ASD Sanity(using ASD)
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Change-Id: I4f403f4b8412ab96cee195412cc412360845b6d0
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This patch makes time window setting to be cleared when disabling
power capping just like others settings.
Change-Id: I3a5fc9c1eb6a5787d131bf69cc18a5dae94a99f0
Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
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This patch makes timestaps catching to happen just after PECI
transaction. It makes reading more accurate since PECI request can hang
while waiting in PECI driver queue.
Change-Id: I1a356caa59148a5cebcfcdf89211038bfadb40d3
Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
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This commit adds an interface for reading chip unique id value.
Optionally, the id can be encrypted using a dts-supplied hash data.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
Change-Id: Ifd98500ea87b3d40e1738e583e077a74851fae35
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When we program TX command register, it requires packet data size in
dwords. Since the aspeed-mctp driver doesn't implement MCTP protocol, it
copies MCTP packet "as it" form userspace and uses size from write()
syscall to program TX command.
If the size from write() doesn't match the payload length in packet PCIe
VDM header, it causes MCTP HW to stop working and we are not able to
reset it without platform power cycle.
To avoid HW issues, let's verify if the data size from write() matches
the payload length in PCIe VDM header.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Change-Id: I6da14babadcc65cb2ba4a2b685495d1baa92c169
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This change adds the SPI region needed for AFM(Attestation
Firmware Manifest) which is used by SPDM Requester in PFR RoT.
The change realigns the remaining flash region and
appends the 256KB AFM region to staging region and reserves
768KB region for PSU and HSBP firmware.
Tested: BMC boot in non-PFR and PFR environment.
Change-Id: I322eebbdbb5dcffbfc45b8b50650ba4aaa5af186
Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com>
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This commit adds a raw value setting interface for uart routing
to provide an atomic way of switching the route.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Change-Id: Id8b80f44f9a503d9f25a692211fc5ec78500ce68
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To support communication with NVDIMM controllers, add definitions for
these I3C devices. Each bus now has two definitions for each DIMM slot.
If populated with a DDR5 DIMM, the SPD Hub device will be used to gather
temperature readings. If populated with an NVDIMM, we'll only need to
talk to the controller sitting behind the hub (local device type 1011b),
to read temperature and use the FW mailbox.
This also removes some logic in the I3C driver which restricts use of
certain addresses due to signal integrity paranoia. An NVDIMM controller
in slot 6 of any bus is blocked by this logic, and unfortunately we
don't have any control over the static address scheme used on the SPD
bus, so the restriction must be removed.
Tested:
Probed I3C busses successfully with DIMMs installed in busses 0 and 1:
$ gpioset $(gpiofind FM_SPD_SWITCH_CTRL_N)=1
$ echo 1e7a2000.i3c0 > /sys/bus/platform/drivers/dw-i3c-master/bind
$ echo 1e7a3000.i3c1 > /sys/bus/platform/drivers/dw-i3c-master/bind
$ ls /dev/i3c*
/dev/i3c-0-3c000000000 /dev/i3c-0-3c000000001 /dev/i3c-0-3c000000002
/dev/i3c-0-3c000000003 /dev/i3c-0-3c000000004 /dev/i3c-0-3c000000005
/dev/i3c-0-3c000000006 /dev/i3c-0-3c000000007 /dev/i3c-0-3c000000008
/dev/i3c-0-3c000000009 /dev/i3c-0-3c00000000a /dev/i3c-0-3c00000000b
/dev/i3c-0-3c00000000c /dev/i3c-0-3c00000000d /dev/i3c-0-3c00000000e
/dev/i3c-1-3c000000000 /dev/i3c-1-3c000000001 /dev/i3c-1-3c000000002
/dev/i3c-1-3c000000003 /dev/i3c-1-3c000000004 /dev/i3c-1-3c000000005
/dev/i3c-1-3c000000006 /dev/i3c-1-3c000000007 /dev/i3c-1-3c000000008
/dev/i3c-1-3c000000009 /dev/i3c-1-3c00000000a /dev/i3c-1-3c00000000b
/dev/i3c-1-3c00000000c /dev/i3c-1-3c00000000d /dev/i3c-1-3c00000000e
Change-Id: I016450edad1ed4ec981500f04122976f1647b8ee
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
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The size of mailbox differ from AST2500, AST2600 A0 and A1. Add an ioctl
support to fetch the mailbox size.
Tested:
Verfied ioctl call returns mailbox size as expected.
Change-Id: I4e261aaf8aa3fb108d6ad152d30a17b114d70ccd
Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
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Using an overshift test environment where we execute a continuous
JTAG R/W operation during hours we discover that in one of million
ocurences for AST26xx TDO read occurred before JTAG Master controller
reflected real tdo value on ASPEED_JTAG_SW.
It was needed to add two delays during the SW xfer process to
prevent this issue. We tested several delay options and found that
using a read/write to ASPEED_JTAG_PADCTRL1(not used in SW mode)
register gives the JTAG Master controller enough time to process
the xfer with the lowest performance impact among the delay options.
For AST25xx an extra delay was not required.
Test:
All of the following in SW mode:
AST26xx(SPR) ASD Sanity finished successfully.
AST26xx(SPR) Overshift test with 4K iterations finished successfully.
AST26xx(SPR) jtag_test with 8M iterations finished successfully.
AST25xx(ICX) ASD Sanity finished successfully
AST25xx(ICX) jtag_test with 8M iterations finished successfully.
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Change-Id: Idf82632a564495e0a69075c9b842e84d39419612
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This commit adds silicon_id sub-node into misc_control node.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Change-Id: I60c09b654ca8a8881e5df4be07f062280210e570
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Modified the Aspeed global driver as a platform driver instead of a
postcore initialized one to make it get a reset control resource
properly while probing the module. To make it probed ahead of bus
modules, it also modifies the object order in makefile.
Change-Id: Icefb06c1a4548417aa09f53da5cb2f61ba6f8d09
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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- Move TDI state matrix to core header file
- These changes are done based on feedback from Paul
Fertser, from the OpenOCD.
Test:
SPR ASD Sanity and jtag_test finished successfully.
ICX ASD Sanity and jtag_test finished successfully.
Change-Id: Idb612e50d5a8ea5929f7c9241d279c345587983a
Signed-off-by: Castro, Omar Eduardo <omar.eduardo.castro@intel.com>
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JTAG xfer length is measured in bits and it is allowed to send non 8-bit
aligned xfers. For such xfers we will read the content of the remaining
bits in the last byte of tdi buffer and restore those bits along with
the xfer readback.
Add also linux types to JTAG header to remove external dependencies.
Test:
SPR ASD Sanity and jtag_test finished successfully.
SKX ASD Sanity and jtag_test finished successfully.
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
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Intel doesn't use transmit clock output of RMII4 module so this
commit customize RMII4 pin ctrl group by removing the F24 pin
setting from RMII4.
This is a downstream customization. Do not upstream it.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Add cleanup fixes after implementing energy sensor for all
modules: cpu, dimm, platform to make all files consistent.
Signed-off-by: Olender, Agata <agata.olender@intel.com>
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Create a low level function to handle xfer interrupts and map
corresponding interrupt functions for AST25xx and AST26xx in
HW1 and HW2 xfer modes.
By default JTAG driver still uses polling. Interrupt support
needs to be enabled with USE_INTERRUPTS macro.
Remove also unused SCU reference.
Test:
AST26xx(SPR) ASD Sanity and jtag_test using HW2 polling.
AST26xx(SPR) ASD Sanity and jtag_test using HW1 polling.
AST26xx(SPR) ASD Sanity and jtag_test using HW2 interrupt.
AST26xx(SPR) ASD Sanity and jtag_test using HW1 interrupt.
AST26xx(SPR) jtag_test using SW mode.
AST25xx(SKX) ASD Sanity and jtag_test using HW polling.
AST25xx(SKX) ASD Sanity and jtag_test using HW interrupt.
AST25xx(SKX) jtag_test using SW mode.
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
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This commit is about disabling reading DRAM_MIN_PWR from
DRAM_POWER_INFO PCS. Starting from SPR DRAM_MIN_PWR is deprecated. BIOS
does not update DRAM min power anymore.
Value of 0 shall be reported as DRAM min power.
Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
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This commit replaces 'Maximal DRAM Power' (MSR@61Ch -
MSR_DRAM_POWER_INFO_HIGH) with the 'Spec DRAM Power'('TDP') (MSR@61Ch -
MSR_DRAM_POWER_INFO_LOW) while maximal DRAM power calculation. This is
to be compliant with SPS ME Node Manager. In case package power it
already works with the same way - TDP is taken as maximal power.
Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
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This commit adds CPU generation info for ICX-D Xeon family.
Signed-off-by: Saravanan Palanisamy <saravanan.palanisamy@intel.com>
Signed-off-by: Anoop S <anoopx.s@intel.com>
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This commit adds CPU generation info for ICX family.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit adds pwm chip driver support into aspeed-g6-pwm-tacho
driver to enable beep speaker driver. The pwm chip driver cannot
be added as a separate platform driver because it makes resource
conflicts with existing pwm-tacho driver so it uses hacky tweak
on the existing driver.
Note: Do not try upstream this hacky implementation.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Change-Id: I22ad12be2ae3a061d7942fec813cdb11be321db7
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Add support for energy consumption of DIMMs sensor.
Energy is reported in micro Joules and exposed under
energyN_input file.
Signed-off-by: Olender, Agata <agata.olender@intel.com>
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The ASPEED BMC SoCs have many knobs and switches that are sometimes
design-specific and often defy any approach to unify them under an
existing subsystem.
Add a driver to translate a devicetree table into sysfs entries to
expose bits and fields for manipulation from userspace. This encompasses
concepts from scratch registers to boolean conditions to enable or
disable host interface features.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Change energy sensor to cumulative energy sensor.
Actually energy sensor implementation works as simply translation for
value read from PCS register to microjoules.
With this change, energy sensor will behave as accumulative sensor>
After every read on energyN_input file new energy sample will be
gathered, and the difference between new sample and previous one will
be added to sensor value.
This approach solves problems with counters overflow and interpretation
of the energy sensor value.
Signed-off-by: Olender, Agata <agata.olender@intel.com>
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Remove modparam to enable peci-mctp probe and enable it by default.
Tested: Verified that peci-mctp driver probes correctly:
peci peci-1: cdev of adapter [peci-mctp] registered as minor 1
Manually verified that applications using PECI work correctly.
Signed-off-by: Karol Wachowski <karol.wachowski@intel.com>
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When peci-mctp finds that there is no discovered CPU, it queries
aspeed-mctp to read BDFs for each static EID reserved by CPU socket.
If BDF is non-zero, peci-mctp reads CPUNODEID_CFG register to determine
CPU represented by this endpoint.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Right now, send and receive API functions are called directly from xfer
handler. Let's add a dedicated helper function responsible for
send/receive to allow issuing PECI messages originated in peci-mctp
driver.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Recently, aspeed-mctp driver functionality was extended to store BDF
values for already discovered MCTP endpoints on PCIe bus.
Let's expose kernel API to read BDF based on endpoint ID.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Support interrupt generation for both 16 and 32 mailbox registers.
Tested:
After applied this patch, write the mailbox registers from BIOS side,
the misc manager can capture the new mailbox data.
Signed-off-by: Yong Li <yong.b.li@linux.intel.com>
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