diff options
| author | Minda Chen <minda.chen@starfivetech.com> | 2023-11-13 11:13:32 +0300 |
|---|---|---|
| committer | Minda Chen <minda.chen@starfivetech.com> | 2023-12-22 06:27:40 +0300 |
| commit | 86c21761bdd54f18efd0e5d01b8c96121d4e2d7c (patch) | |
| tree | 94f8677c272b67cf6701fc58a096b4dce594ba09 | |
| parent | 982362719a6c83c192c4aa0166f177772ba4b2fa (diff) | |
| download | linux-86c21761bdd54f18efd0e5d01b8c96121d4e2d7c.tar.xz | |
clk: set uart1 clock keep openning
Do not disable uart1 clock while kernel init.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
| -rw-r--r-- | drivers/clk/starfive/clk-starfive-jh7110-sys.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c index 0a9d0f7b32b2..5df3bf8c494e 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -356,9 +356,9 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = { JH7110_GATE(JH7110_UART0_CLK_CORE, "u0_dw_uart_clk_core", CLK_IGNORE_UNUSED, JH7110_OSC), JH7110_GATE(JH7110_UART1_CLK_APB, "u1_dw_uart_clk_apb", - GATE_FLAG_NORMAL, JH7110_APB0), + CLK_IGNORE_UNUSED, JH7110_APB0), JH7110_GATE(JH7110_UART1_CLK_CORE, "u1_dw_uart_clk_core", - GATE_FLAG_NORMAL, JH7110_OSC), + CLK_IGNORE_UNUSED, JH7110_OSC), JH7110_GATE(JH7110_UART2_CLK_APB, "u2_dw_uart_clk_apb", GATE_FLAG_NORMAL, JH7110_APB0), JH7110_GATE(JH7110_UART2_CLK_CORE, "u2_dw_uart_clk_core", |