riscv: dts: starfive: dubhe: Restructure Dubhe device tree

Restructure the Dubhe device tree in preparation for Dubhe 80 support.
Rename existing Dubhe to Dubhe 90.

Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>

5 files changed, 33 insertions, 21 deletions

diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 9374f075c70e..fb2208c09d9b 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
-dtb-$(CONFIG_SOC_STARFIVE_DUBHE) += dubhe_fpga.dtb dubhe_fpga_dual.dtb
+dtb-$(CONFIG_SOC_STARFIVE_DUBHE) += dubhe90_fpga.dtb dubhe90_fpga_dual.dtb
diff --git a/arch/riscv/boot/dts/starfive/dubhe.dtsi b/arch/riscv/boot/dts/starfive/dubhe.dtsi
index 95caf3cbf794..246e8bc69e64 100755
--- a/arch/riscv/boot/dts/starfive/dubhe.dtsi
+++ b/arch/riscv/boot/dts/starfive/dubhe.dtsi
@@ -12,21 +12,14 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "starfive,dubhe", "riscv";
-			d-cache-block-size = <64>;
-			d-cache-sets = <128>;
-			d-cache-size = <65536>;
 			device_type = "cpu";
-			i-cache-block-size = <64>;
-			i-cache-sets = <512>;
-			i-cache-size = <65536>;
-			i-tlb-sets = <1>;
-			i-tlb-size = <32>;
 			mmu-type = "riscv,sv48";
 			reg = <0x0>;
 			riscv,isa = "rv64imafdcbhn_sscofpmf";
 			tlb-split;
+
 			cpu0_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -34,21 +27,14 @@
 			};
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "starfive,dubhe", "riscv";
-			d-cache-block-size = <64>;
-			d-cache-sets = <128>;
-			d-cache-size = <65536>;
 			device_type = "cpu";
-			i-cache-block-size = <64>;
-			i-cache-sets = <512>;
-			i-cache-size = <65536>;
-			i-tlb-sets = <1>;
-			i-tlb-size = <32>;
 			mmu-type = "riscv,sv48";
 			reg = <0x1>;
 			riscv,isa = "rv64imafdcbhn_sscofpmf";
 			tlb-split;
+
 			cpu1_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
diff --git a/arch/riscv/boot/dts/starfive/dubhe90.dtsi b/arch/riscv/boot/dts/starfive/dubhe90.dtsi
new file mode 100644
index 000000000000..1f52a39257fb
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/dubhe90.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
+
+#include "dubhe.dtsi"
+
+&cpu0 {
+        d-cache-block-size = <64>;
+        d-cache-sets = <128>;
+        d-cache-size = <65536>;
+        i-cache-block-size = <64>;
+        i-cache-sets = <512>;
+        i-cache-size = <65536>;
+        i-tlb-sets = <1>;
+        i-tlb-size = <32>;
+};
+
+&cpu1 {
+        d-cache-block-size = <64>;
+        d-cache-sets = <128>;
+        d-cache-size = <65536>;
+        i-cache-block-size = <64>;
+        i-cache-sets = <512>;
+        i-cache-size = <65536>;
+        i-tlb-sets = <1>;
+        i-tlb-size = <32>;
+};
diff --git a/arch/riscv/boot/dts/starfive/dubhe_fpga.dts b/arch/riscv/boot/dts/starfive/dubhe90_fpga.dts
index 879d11946631..d18aebd140fe 100755..100644
--- a/arch/riscv/boot/dts/starfive/dubhe_fpga.dts
+++ b/arch/riscv/boot/dts/starfive/dubhe90_fpga.dts
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /* Copyright (c) 2021 StarFive Technology Co., Ltd. */
 
-#include "dubhe.dtsi"
+#include "dubhe90.dtsi"
 
 / {
 	model = "StarFive Dubhe FPGA";
diff --git a/arch/riscv/boot/dts/starfive/dubhe_fpga_dual.dts b/arch/riscv/boot/dts/starfive/dubhe90_fpga_dual.dts
index 86d69ea6c73b..cab2dddbde40 100644
--- a/arch/riscv/boot/dts/starfive/dubhe_fpga_dual.dts
+++ b/arch/riscv/boot/dts/starfive/dubhe90_fpga_dual.dts
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /* Copyright (c) 2022 StarFive Technology Co., Ltd. */
 
-#include "dubhe.dtsi"
+#include "dubhe90.dtsi"
 
 / {
 	model = "StarFive Dubhe Dual-FPGA";