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| author | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2023-10-27 18:15:26 +0300 |
|---|---|---|
| committer | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2023-12-04 06:00:17 +0300 |
| commit | 55edd9b050cc9e14b4a7919d49b64f7e5ae6df96 (patch) | |
| tree | 91fde405b8a2385ffcfa30f838a6294aee23f290 | |
| parent | ad8d0c28f8f4f2f4eaad50c8389a26e52ca684c6 (diff) | |
| download | linux-55edd9b050cc9e14b4a7919d49b64f7e5ae6df96.tar.xz | |
riscv: dts: starfive: Convert spaces to tabs
Fix warning from checkpatch.pl.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe80.dtsi | 40 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe90.dtsi | 42 |
2 files changed, 41 insertions, 41 deletions
diff --git a/arch/riscv/boot/dts/starfive/dubhe80.dtsi b/arch/riscv/boot/dts/starfive/dubhe80.dtsi index b6dfb850e870..2eeb2d28655c 100644 --- a/arch/riscv/boot/dts/starfive/dubhe80.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe80.dtsi @@ -4,27 +4,27 @@ #include "dubhe.dtsi" &cpu0 { - d-cache-block-size = <64>; - d-cache-sets = <512>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <48>; - i-cache-block-size = <64>; - i-cache-sets = <512>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <48>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <48>; }; &cpu1 { - d-cache-block-size = <64>; - d-cache-sets = <512>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <48>; - i-cache-block-size = <64>; - i-cache-sets = <512>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <48>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <48>; }; diff --git a/arch/riscv/boot/dts/starfive/dubhe90.dtsi b/arch/riscv/boot/dts/starfive/dubhe90.dtsi index 3beec1dde13b..54297ca6d805 100644 --- a/arch/riscv/boot/dts/starfive/dubhe90.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe90.dtsi @@ -4,27 +4,27 @@ #include "dubhe.dtsi" &cpu0 { - d-cache-block-size = <64>; - d-cache-sets = <1024>; - d-cache-size = <65536>; - d-tlb-sets = <1>; - d-tlb-size = <48>; - i-cache-block-size = <64>; - i-cache-sets = <1024>; - i-cache-size = <65536>; - i-tlb-sets = <1>; - i-tlb-size = <48>; -}; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + }; &cpu1 { - d-cache-block-size = <64>; - d-cache-sets = <1024>; - d-cache-size = <65536>; - d-tlb-sets = <1>; - d-tlb-size = <48>; - i-cache-block-size = <64>; - i-cache-sets = <1024>; - i-cache-size = <65536>; - i-tlb-sets = <1>; - i-tlb-size = <48>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; }; |