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| author | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2023-08-30 11:19:55 +0300 |
|---|---|---|
| committer | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2023-12-04 06:00:16 +0300 |
| commit | e10d7497271e632dac75ee4c38bab5a13cdab61d (patch) | |
| tree | 2cfacd7cab11408ae16a21db248f8aecf2c63ab7 | |
| parent | 172e521c11fc14101ee17bf37906d7caeb15777b (diff) | |
| download | linux-e10d7497271e632dac75ee4c38bab5a13cdab61d.tar.xz | |
riscv: dts: starfive: dubhe: Update Dubhe90 cpu DT node
- Add cpu0 and cpu1 label
- Update D cache and I cache settings
- Update "riscv,isa", remove unused 'n'.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
| -rwxr-xr-x | arch/riscv/boot/dts/starfive/dubhe.dtsi | 4 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe90.dtsi | 16 |
2 files changed, 12 insertions, 8 deletions
diff --git a/arch/riscv/boot/dts/starfive/dubhe.dtsi b/arch/riscv/boot/dts/starfive/dubhe.dtsi index 246e8bc69e64..53465859b661 100755 --- a/arch/riscv/boot/dts/starfive/dubhe.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe.dtsi @@ -17,7 +17,7 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; reg = <0x0>; - riscv,isa = "rv64imafdcbhn_sscofpmf"; + riscv,isa = "rv64imafdcbh_sscofpmf"; tlb-split; cpu0_intc: interrupt-controller { @@ -32,7 +32,7 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; reg = <0x1>; - riscv,isa = "rv64imafdcbhn_sscofpmf"; + riscv,isa = "rv64imafdcbh_sscofpmf"; tlb-split; cpu1_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/starfive/dubhe90.dtsi b/arch/riscv/boot/dts/starfive/dubhe90.dtsi index 1f52a39257fb..3beec1dde13b 100644 --- a/arch/riscv/boot/dts/starfive/dubhe90.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe90.dtsi @@ -5,22 +5,26 @@ &cpu0 { d-cache-block-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <1024>; d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; i-cache-block-size = <64>; - i-cache-sets = <512>; + i-cache-sets = <1024>; i-cache-size = <65536>; i-tlb-sets = <1>; - i-tlb-size = <32>; + i-tlb-size = <48>; }; &cpu1 { d-cache-block-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <1024>; d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; i-cache-block-size = <64>; - i-cache-sets = <512>; + i-cache-sets = <1024>; i-cache-size = <65536>; i-tlb-sets = <1>; - i-tlb-size = <32>; + i-tlb-size = <48>; }; |