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authorLey Foon Tan <leyfoon.tan@starfivetech.com>2023-10-25 09:22:01 +0300
committerLey Foon Tan <leyfoon.tan@starfivetech.com>2023-12-04 06:00:13 +0300
commitf9e9e8f8144aacea6e4ebcdd29262901f19a91fc (patch)
tree49c5ba0e68e9a0505f02cee320d42b3a9a6e1f3a
parentbfe346d0d59f6318d1e224b88ade8e3832a7a6d2 (diff)
downloadlinux-f9e9e8f8144aacea6e4ebcdd29262901f19a91fc.tar.xz
riscv: sbi: Add support for sbi_cache_flush and sbi_cache_invalidate
This patch introduces the support for GMAC drivers to perform flush and invalidate of L2 Cache: * sbi_cache_invalidate(): Invalidate L2 cache for data passed from GMAC to CPU * sbi_cache_flush(): Flush L2 cache for data passed from CPU to GMAC Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
-rw-r--r--arch/riscv/include/asm/sbi.h9
-rw-r--r--arch/riscv/kernel/sbi.c29
2 files changed, 38 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 9baddaee5623..043a56cc90c0 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -37,6 +37,7 @@ enum sbi_ext_id {
/* Vendor extensions must lie within this range */
SBI_EXT_VENDOR_START = 0x09000000,
+ SBI_EXT_CACHE = 0x09057485,
SBI_EXT_VENDOR_END = 0x09FFFFFF,
};
@@ -137,6 +138,12 @@ union sbi_pmu_ctr_info {
};
#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)
+
+enum sbi_ext_cache_fid {
+ SBI_EXT_BASE_L2_FLUSH = 0,
+ SBI_EXT_BASE_L2_INVALIDATE,
+};
+
#define RISCV_PMU_RAW_EVENT_IDX 0x20000
/** General pmu event codes specified in SBI PMU extension */
@@ -294,6 +301,8 @@ int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
unsigned long size,
unsigned long asid);
long sbi_probe_extension(int ext);
+int sbi_cache_invalidate(unsigned long start, unsigned long len);
+int sbi_cache_flush(unsigned long start, unsigned long len);
/* Check if current SBI specification version is 0.1 or not */
static inline int sbi_spec_is_0_1(void)
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index ef4af31ed2e8..e7b14f0f7032 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -649,6 +649,35 @@ static const struct riscv_ipi_ops sbi_ipi_ops = {
.ipi_inject = sbi_send_cpumask_ipi
};
+int sbi_cache_flush(unsigned long start, unsigned long len)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_CACHE, SBI_EXT_BASE_L2_FLUSH,
+ start, len, 0, 0, 0, 0);
+ if (!ret.error)
+ if (ret.value)
+ return ret.value;
+
+ return -ENOTSUPP;
+}
+EXPORT_SYMBOL(sbi_cache_flush);
+
+int sbi_cache_invalidate(unsigned long start, unsigned long len)
+{
+
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_CACHE, SBI_EXT_BASE_L2_INVALIDATE,
+ start, len, 0, 0, 0, 0);
+ if (!ret.error)
+ if (ret.value)
+ return ret.value;
+
+ return -ENOTSUPP;
+}
+EXPORT_SYMBOL(sbi_cache_invalidate);
+
void __init sbi_init(void)
{
int ret;