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| author | Bin Meng <bmeng.cn@gmail.com> | 2021-06-04 18:35:43 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-06-11 08:48:07 +0300 |
| commit | b32fac4b65aabcd5fb555a87fcd94b4f2e297357 (patch) | |
| tree | 14b01b07bbd76202dc51b097bbfcc762bfe78b3e | |
| parent | a03ea2e2b1e5e81c018c4ebcce34e241eb2c6b90 (diff) | |
| download | opensbi-b32fac4b65aabcd5fb555a87fcd94b4f2e297357.tar.xz | |
docs/platform: andes-ae350: Fix missing spaces
Fix several places in the docmentation that are missing spaces.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
| -rw-r--r-- | docs/platform/andes-ae350.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/platform/andes-ae350.md b/docs/platform/andes-ae350.md index 46889a1..1cf83cf 100644 --- a/docs/platform/andes-ae350.md +++ b/docs/platform/andes-ae350.md @@ -1,9 +1,9 @@ Andes AE350 SoC Platform ======================== The AE350 AXI/AHB-based platform N25(F)/NX25(F)/D25F/A25/AX25 CPU with level-one -memories,interrupt controller, debug module, AXI and AHB Bus Matrix Controller, -AXI-to-AHB Bridge and a collection of fundamentalAHB/APB bus IP components -pre-integrated together as a system design.The high-quality and configurable +memories, interrupt controller, debug module, AXI and AHB Bus Matrix Controller, +AXI-to-AHB Bridge and a collection of fundamental AHB/APB bus IP components +pre-integrated together as a system design. The high-quality and configurable AHB/APB IPs suites a majority embedded systems, and the verified platform serves as a starting point to jump start SoC designs. |