diff options
| author | Atish Patra <atish.patra@wdc.com> | 2021-07-10 19:18:09 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2021-07-11 07:50:44 +0300 |
| commit | 49966db30658a3d5070e1a10200bd8c73dab0851 (patch) | |
| tree | d74530cded4b0071f4821d5fc7fded6b52069c45 | |
| parent | fd9116bd46e59ef8fbeaa147bb102527635615ba (diff) | |
| download | opensbi-49966db30658a3d5070e1a10200bd8c73dab0851.tar.xz | |
lib: sbi: Use csr_read/write_num to read/update PMU counters
Currently, csr_read/write_num functions are used to read/write PMP related
CSRs where CSR value is decided at runtime. Expand this function to include
PMU related CSRs as well.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
| -rw-r--r-- | lib/sbi/riscv_asm.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index 8c54c11..4c24a51 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -118,6 +118,21 @@ unsigned long csr_read_num(int csr_num) switch (csr_num) { switchcase_csr_read_16(CSR_PMPCFG0, ret) switchcase_csr_read_64(CSR_PMPADDR0, ret) + switchcase_csr_read(CSR_MCYCLE, ret) + switchcase_csr_read(CSR_MINSTRET, ret) + switchcase_csr_read(CSR_MHPMCOUNTER3, ret) + switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret) + switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret) + switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret) +#if __riscv_xlen == 32 + switchcase_csr_read(CSR_MCYCLEH, ret) + switchcase_csr_read(CSR_MINSTRETH, ret) + switchcase_csr_read(CSR_MHPMCOUNTER3H, ret) + switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret) + switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret) + switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret) +#endif + default: break; }; @@ -161,6 +176,26 @@ void csr_write_num(int csr_num, unsigned long val) switch (csr_num) { switchcase_csr_write_16(CSR_PMPCFG0, val) switchcase_csr_write_64(CSR_PMPADDR0, val) + switchcase_csr_write(CSR_MCYCLE, val) + switchcase_csr_write(CSR_MINSTRET, val) + switchcase_csr_write(CSR_MHPMCOUNTER3, val) + switchcase_csr_write_4(CSR_MHPMCOUNTER4, val) + switchcase_csr_write_8(CSR_MHPMCOUNTER8, val) + switchcase_csr_write_16(CSR_MHPMCOUNTER16, val) +#if __riscv_xlen == 32 + switchcase_csr_write(CSR_MCYCLEH, val) + switchcase_csr_write(CSR_MINSTRETH, val) + switchcase_csr_write(CSR_MHPMCOUNTER3H, val) + switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val) + switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val) + switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val) +#endif + switchcase_csr_write(CSR_MCOUNTINHIBIT, val) + switchcase_csr_write(CSR_MHPMEVENT3, val) + switchcase_csr_write_4(CSR_MHPMEVENT4, val) + switchcase_csr_write_8(CSR_MHPMEVENT8, val) + switchcase_csr_write_16(CSR_MHPMEVENT16, val) + default: break; }; |