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| author | dramforever <dramforever@live.com> | 2022-06-09 10:07:29 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-06-21 06:01:04 +0300 |
| commit | 551c70c0405b98ae75698d1674c9e0e09fdc6e01 (patch) | |
| tree | f518833e7934d9b9e32c13e19ea12837ad9f827d | |
| parent | 9dc5ec5c519b2ec1702e13a97b9e595ee5d94bf6 (diff) | |
| download | opensbi-551c70c0405b98ae75698d1674c9e0e09fdc6e01.tar.xz | |
include: sbi: Add mtinst/htinst psuedoinstructions
Add psuedoinstruction encodings written to mtinst/htinst for faults
caused by implicit memory access for VS-stage address translation
Signed-off-by: dramforever <dramforever@live.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | include/sbi/riscv_encoding.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index a164768..2292858 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -841,6 +841,26 @@ #define INSN_MASK_FENCE_TSO 0xffffffff #define INSN_MATCH_FENCE_TSO 0x8330000f +#if __riscv_xlen == 64 + +/* 64-bit read for VS-stage address translation (RV64) */ +#define INSN_PSEUDO_VS_LOAD 0x00003000 + +/* 64-bit write for VS-stage address translation (RV64) */ +#define INSN_PSEUDO_VS_STORE 0x00003020 + +#elif __riscv_xlen == 32 + +/* 32-bit read for VS-stage address translation (RV32) */ +#define INSN_PSEUDO_VS_LOAD 0x00002000 + +/* 32-bit write for VS-stage address translation (RV32) */ +#define INSN_PSEUDO_VS_STORE 0x00002020 + +#else +#error "Unexpected __riscv_xlen" +#endif + #define INSN_16BIT_MASK 0x3 #define INSN_32BIT_MASK 0x1c |