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authorGenevieve Chan <genevieve.chan@starfivetech.com>2023-05-18 11:28:45 +0300
committerGenevieve Chan <genevieve.chan@starfivetech.com>2023-05-18 11:29:03 +0300
commit6aeb74b1711c9b1e57520b6d609ad1e86dff521d (patch)
tree3e5bbe8e34deb756e4a4e9faec11fe3a9450b8bb
parentdf3de2f059c8c7edd1ba48ea43e6d8b93553a58a (diff)
downloadopensbi-6aeb74b1711c9b1e57520b6d609ad1e86dff521d.tar.xz
platform: generic: starfive: Remove CFLUSH.L2 in __sbi_dubhe_L2_inv_range
CFLUSH.L2 does not checks for dirty bits before performing flush. Instead, CFLUSH.L2 will always flush once the instruction is called. Remove CFLUSH.L2 from this function to prevent the new data in DDR to be overwritten with old data from L2 cache. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
-rwxr-xr-xplatform/generic/starfive/dubhe_cache.S28
1 files changed, 5 insertions, 23 deletions
diff --git a/platform/generic/starfive/dubhe_cache.S b/platform/generic/starfive/dubhe_cache.S
index d0b3f94..9ab8895 100755
--- a/platform/generic/starfive/dubhe_cache.S
+++ b/platform/generic/starfive/dubhe_cache.S
@@ -21,38 +21,20 @@
.align 3
.global __sbi_dubhe_L2_inv_range
__sbi_dubhe_L2_inv_range:
- beqz a1, 4f
+ beqz a1, 2f
li t0, DUBHE_L2_CACHELINE_SIZE
addi t1, t0, -1
add a1, a1, a0 /* Compute end address */
- and t2, a0, t1
- not t3, t1
- and a0, a0, t3
- beqz t2, 1f
- /* CFLUSH.L2 rs1 = a0 */
- fence rw, rw
- .insn i 0x73, 0, x0, a0, -0x3C
- fence rw, rw
- add a0, a0, t0
+ not t2, t1
+ and a0, a0, t2
1:
- and t2, a1, t1
- not t3, t1
- and a1, a1, t3
- beqz t2, 2f
- /* CFLUSH.L2 rs1 = a1 */
- fence rw, rw
- .insn i 0x73, 0, x0, a1, -0x3C
- fence rw, rw
-2:
- bge a0, a1, 4f
-3:
/* CDISCARD.L2 rs1 = a0 */
fence rw, rw
.insn i 0x73, 0, x0, a0, -0x3A
fence rw, rw
add a0, a0, t0
- blt a0, a1, 3b
-4:
+ blt a0, a1, 1b
+2:
ret
/*