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| author | Samuel Holland <samuel@sholland.org> | 2021-10-20 04:58:38 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-06-21 06:50:59 +0300 |
| commit | 7738345396fbbae543a5af14fbc965d9163c12a0 (patch) | |
| tree | 134b49530b8d6cb4cf928384fd8f960eff9d50ad /docs | |
| parent | c6530012d46ed9c9655c426450bfa3aabcc0eadd (diff) | |
| download | opensbi-7738345396fbbae543a5af14fbc965d9163c12a0.tar.xz | |
lib: utils/timer: Add a separate compatible for the D1 CLINT
The CLINT in the Allwinner D1 SoC apparently does not support 64-bit
MMIO access. A property was added to support this quirk (and that
property was copied to the ACLINT MTIMER code). However, since this
difference in behavior makes the D1 CLINT incompatible with the SiFive
CLINT's programming interface, a better solution is to use a separate
compatible string.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/platform/thead-c9xx.md | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/docs/platform/thead-c9xx.md b/docs/platform/thead-c9xx.md index 3490ed5..ced784d 100644 --- a/docs/platform/thead-c9xx.md +++ b/docs/platform/thead-c9xx.md @@ -52,12 +52,11 @@ DTS Example1: (Single core, eg: Allwinner D1 - c906) ranges; clint0: clint@14000000 { - compatible = "riscv,clint0"; + compatible = "allwinner,sun20i-d1-clint"; interrupts-extended = < &cpu0_intc 3 &cpu0_intc 7 >; reg = <0x0 0x14000000 0x0 0x04000000>; - clint,has-no-64bit-mmio; }; intc: interrupt-controller@10000000 { @@ -163,7 +162,6 @@ DTS Example2: (Multi cores with soc reset-regs) &cpu4_intc 3 &cpu4_intc 7 >; reg = <0xff 0xdc000000 0x0 0x04000000>; - clint,has-no-64bit-mmio; }; intc: interrupt-controller@ffd8000000 { |