diff options
| author | Mayuresh Chitale <mchitale@ventanamicro.com> | 2023-03-09 16:13:58 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-03-10 11:30:33 +0300 |
| commit | c631a7da279e735590231d2ae432fbc05743aa9e (patch) | |
| tree | f5567d75186a10e14335593603f9c36a932b1c31 /include | |
| parent | 57d3aa3b0dbd534ab702dce61767df0e9dc7577f (diff) | |
| download | opensbi-c631a7da279e735590231d2ae432fbc05743aa9e.tar.xz | |
lib: sbi_pmu: Add hartid parameter PMU device ops
Platform specific firmware event handler may leverage the hartid to program
per hart specific registers for a given counter.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sbi/sbi_pmu.h | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index 53f2700..16f6877 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -31,13 +31,14 @@ struct sbi_pmu_device { /** * Validate event code of custom firmware event */ - int (*fw_event_validate_encoding)(uint64_t event_data); + int (*fw_event_validate_encoding)(uint32_t hartid, uint64_t event_data); /** * Match custom firmware counter with custom firmware event * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ - bool (*fw_counter_match_encoding)(uint32_t counter_index, + bool (*fw_counter_match_encoding)(uint32_t hartid, + uint32_t counter_index, uint64_t event_data); /** @@ -49,27 +50,28 @@ struct sbi_pmu_device { * Read value of custom firmware counter * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ - uint64_t (*fw_counter_read_value)(uint32_t counter_index); + uint64_t (*fw_counter_read_value)(uint32_t hartid, + uint32_t counter_index); /** * Write value to custom firmware counter * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ - void (*fw_counter_write_value)(uint32_t counter_index, + void (*fw_counter_write_value)(uint32_t hartid, uint32_t counter_index, uint64_t value); /** * Start custom firmware counter * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ - int (*fw_counter_start)(uint32_t counter_index, + int (*fw_counter_start)(uint32_t hartid, uint32_t counter_index, uint64_t event_data); /** * Stop custom firmware counter * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ - int (*fw_counter_stop)(uint32_t counter_index); + int (*fw_counter_stop)(uint32_t hartid, uint32_t counter_index); /** * Custom enable irq for hardware counter |