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| author | jianlong.huang <jianlong.huang@starfivetech.com> | 2022-04-27 05:29:05 +0300 |
|---|---|---|
| committer | jianlong.huang <jianlong.huang@starfivetech.com> | 2022-04-27 05:29:05 +0300 |
| commit | 48e83a7af5c2bcf8262a561649d1702d07bc69de (patch) | |
| tree | de0a7114d98951abeeca549e76d3ec601da36eef | |
| parent | e095428f8aaef8b317c352e42972111e0d44b75d (diff) | |
| download | u-boot-48e83a7af5c2bcf8262a561649d1702d07bc69de.tar.xz | |
add starfive timer initVF_SDK_510_V1.0.2
Signed-off-by: jianlong.huang <jianlong.huang@starfivetech.com>
| -rw-r--r-- | board/starfive/jh7100/jh7100.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/board/starfive/jh7100/jh7100.c b/board/starfive/jh7100/jh7100.c index bf59cc32dc..286e00dbd8 100644 --- a/board/starfive/jh7100/jh7100.c +++ b/board/starfive/jh7100/jh7100.c @@ -1096,6 +1096,28 @@ INIT_FUNC_DEF(i2c3) _CLEAR_RESET_rstgen_rstn_i2c3_core_; } +INIT_FUNC_DEF(timer) +{ + _ENABLE_CLOCK_clk_wdtimer_apb_; + + _ENABLE_CLOCK_clk_timer0_coreclk_; + _ENABLE_CLOCK_clk_timer1_coreclk_; + _ENABLE_CLOCK_clk_timer2_coreclk_; + _ENABLE_CLOCK_clk_timer3_coreclk_; + _ENABLE_CLOCK_clk_timer4_coreclk_; + _ENABLE_CLOCK_clk_timer5_coreclk_; + _ENABLE_CLOCK_clk_timer6_coreclk_; + + //_CLEAR_RESET_rstgen_rstn_wdtimer_apb_; + _CLEAR_RESET_rstgen_rstn_timer0_; + _CLEAR_RESET_rstgen_rstn_timer1_; + _CLEAR_RESET_rstgen_rstn_timer2_; + _CLEAR_RESET_rstgen_rstn_timer3_; + _CLEAR_RESET_rstgen_rstn_timer4_; + _CLEAR_RESET_rstgen_rstn_timer5_; + _CLEAR_RESET_rstgen_rstn_timer6_; +} + /* disable, when we don't realy use it */ #if 0 INIT_FUNC_DEF(wdt) @@ -1355,6 +1377,7 @@ int board_hw_init(void) // INIT_FUNC_CALL(uart3); INIT_FUNC_CALL(i2c2); INIT_FUNC_CALL(i2c3); + INIT_FUNC_CALL(timer); // INIT_FUNC_CALL(wdt); INIT_FUNC_CALL(ptc); |