diff options
author | woonjiet.chong <woonjiet.chong@starfivetech.com> | 2021-09-02 06:23:13 +0300 |
---|---|---|
committer | Wei Liang Lim <weiliang.lim@starfivetech.com> | 2023-10-18 09:04:24 +0300 |
commit | 1813fb1b66bdea66c7cf3073ab033ba5271888fb (patch) | |
tree | 595602758d45e72147bd7848c54a3ff7f044b573 | |
parent | 4459ed60cb1e0562bc5b40405e2b4b9bbf766d57 (diff) | |
download | u-boot-1813fb1b66bdea66c7cf3073ab033ba5271888fb.tar.xz |
Enable SPL, OpenSBI and U-Boot proper boot flow for Dubhe FPGA
-rwxr-xr-x[-rw-r--r--] | arch/riscv/Kconfig | 4 | ||||
-rwxr-xr-x[-rw-r--r--] | arch/riscv/dts/Makefile | 1 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe-fpga-u-boot.dtsi | 128 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe.dtsi | 102 | ||||
-rw-r--r-- | arch/riscv/dts/dubhe_fpga.dts | 88 | ||||
-rw-r--r-- | board/starfive/dubhe_fpga/Kconfig | 38 | ||||
-rw-r--r-- | board/starfive/dubhe_fpga/MAINTAINERS | 5 | ||||
-rw-r--r-- | board/starfive/dubhe_fpga/Makefile | 5 | ||||
-rwxr-xr-x | board/starfive/dubhe_fpga/dubhe_fpga.c | 7 | ||||
-rwxr-xr-x | board/starfive/dubhe_fpga/dubhe_fpga_spl.c | 19 | ||||
-rw-r--r-- | configs/starfive_dubhe_fpga_defconfig | 39 | ||||
-rwxr-xr-x[-rw-r--r--] | drivers/mtd/spi/spi-nor-ids.c | 2 | ||||
-rw-r--r-- | include/configs/starfive-dubhe-fpga.h | 16 |
13 files changed, 454 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 1c62c2345b..bfed12dbca 100644..100755 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -39,6 +39,9 @@ config TARGET_SIPEED_MAIX config TARGET_OPENPITON_RISCV64 bool "Support RISC-V cores on OpenPiton SoC" +config TARGET_STARFIVE_DUBHE_FPGA + bool "Support StarFive Dubhe FPGA Board" + endchoice config SYS_ICACHE_OFF @@ -83,6 +86,7 @@ source "board/thead/th1520_lpi4a/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" +source "board/starfive/dubhe_fpga/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f1525cb668..5b6bf2e588 100644..100755 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts +dtb-$(CONFIG_TARGET_STARFIVE_DUBHE_FPGA) += dubhe_fpga.dtb targets += $(dtb-y) diff --git a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi new file mode 100644 index 0000000000..39f452d48c --- /dev/null +++ b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2021 StarFive Technology Co., Ltd. */ + +/ { + chosen { + stdout-path = "serial0"; + }; + + config { + u-boot,spl-payload-offset = <0x22000>; + }; + + cpus { + u-boot,dm-spl; + cpu@0 { + u-boot,dm-spl; + }; + }; + + memory@80000000 { + u-boot,dm-spl; + }; + + soc { + u-boot,dm-spl; + }; +}; + +&spi0 { + u-boot,dm-spl; +}; + +&qspi1 { + u-boot,dm-spl; + + flash@0 { + u-boot,dm-spl; + }; +}; + +&binman { + kernel_fit { + filename = "kernel.itb"; + fit { + description = "FIT with Linux kernel image and FDT"; + #address-cells = <1>; + images { + kernel { + description = "Linux kernel"; + type = "kernel"; + arch = "riscv"; + os = "linux"; + compression = "none"; + load = <0x80200000>; + entry = <0x80200000>; + kernel_blob: blob-ext { + filename = "Image"; + }; + }; + fdt_kernel { + description = "Linux kernel device tree binary"; + type = "flat_dt"; + arch = "riscv"; + compression = "none"; + load = <0x88000000>; + fdt_kernel_blob: blob-ext { + filename = "dubhe_fpga_linux.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + conf { + description = "Starfive Dubhe FPGA"; + kernel = "kernel"; + fdt = "fdt_kernel"; + }; + }; + }; + }; + + QSPI_Image_binary { + filename = "QSPI-Image.bin"; + pad-byte = <0xff>; + + bootcopier_blob: blob-ext@0 { + filename = "dubhe_fpga_bootcode.bin"; + offset = <0x0>; + }; + + bootjump_blob: blob-ext@1 { + filename = "dubhe_fpga_bootjump.bin"; + offset = <0x1000>; + }; + + u-boot-spl { + offset = <0x2000>; + }; + + qspi_ubootproper_opensbi_blob: blob-ext@2 { + filename = "u-boot.itb"; + offset = <0x22000>; + }; + + qspi_kernel_blob: blob-ext@3 { + filename = "kernel.itb"; + offset = <0x400000>; + }; + }; +}; + +&uart0 { + u-boot,dm-spl; +}; + +&pbus_clk { + u-boot,dm-spl; +}; + +&clint { + clocks = <&pbus_clk>; + u-boot,dm-spl; +}; + +&cpu0_intc { + u-boot,dm-spl; +}; diff --git a/arch/riscv/dts/dubhe.dtsi b/arch/riscv/dts/dubhe.dtsi new file mode 100644 index 0000000000..f689389c73 --- /dev/null +++ b/arch/riscv/dts/dubhe.dtsi @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2021 StarFive Technology Co., Ltd. */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "starfive,dubhe"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "starfive,dubhe0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <128>; + d-cache-size = <65536>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv48"; + reg = <0x0>; + riscv,isa = "rv64imafdcbhnv"; + tlb-split; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + clint: clint@2000000 { + #interrupt-cells = <1>; + compatible = "riscv,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, + <&cpu0_intc 7>; + }; + + pbus_clk: subsystem_pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,max-priority = <15>; + riscv,ndev = <25>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, + <&cpu0_intc 9>; + }; + + spi0: spi@10000000 { + compatible = "sifive,spi0"; + reg = <0x0 0x10000000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <7>; + clocks = <&pbus_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi1: spi@10010000 { + compatible = "sifive,spi0"; + reg = <0x0 0x10010000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x8000000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&pbus_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@10012000 { + compatible = "sifive,uart0"; + interrupt-parent = <&plic0>; + interrupts = <5>; + reg = <0x0 0x10012000 0x0 0x1000>; + clocks = <&pbus_clk>; + status = "disabled"; + }; + }; +}; diff --git a/arch/riscv/dts/dubhe_fpga.dts b/arch/riscv/dts/dubhe_fpga.dts new file mode 100644 index 0000000000..21a487b4e7 --- /dev/null +++ b/arch/riscv/dts/dubhe_fpga.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2021 StarFive Technology Co., Ltd. */ + +#include "dubhe.dtsi" +#include "binman.dtsi" +#include "dubhe-fpga-u-boot.dtsi" + +/ { + model = "StarFive Dubhe FPGA"; + + aliases { + serial0 = &uart0; + }; + + chosen { + bootargs = "console=ttySIF0,115200 earlycon=sbi root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"; + }; + + cpus { + timebase-frequency = <25000000>; + + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x0>; + }; + + soc { + }; +}; + +&spi0 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +&qspi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + m25p,fast-read; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x000000 0x1000>; + label = "boot copier"; + /*read-only;*/ + }; + + partition@1000 { + reg = <0x1000 0x1000>; + label = "boot jump"; + /*read-only;*/ + }; + + partition@2000 { + reg = <0x2000 0x2000>; + label = "DTB"; + }; + + partition@4000 { + reg = <0x4000 0x7ffc000>; + label = "FW_payload (OpenSBI and Linux)"; + }; + }; + }; + +}; + +&uart0 { + status = "okay"; +}; diff --git a/board/starfive/dubhe_fpga/Kconfig b/board/starfive/dubhe_fpga/Kconfig new file mode 100644 index 0000000000..6852cec4d6 --- /dev/null +++ b/board/starfive/dubhe_fpga/Kconfig @@ -0,0 +1,38 @@ +if TARGET_STARFIVE_DUBHE_FPGA + +config SYS_CPU + default "generic" + +config SYS_BOARD + default "dubhe_fpga" + +config SYS_VENDOR + default "starfive" + +config SYS_SOC + default "dubhe_fpga_soc" + +config SYS_CONFIG_NAME + default "starfive-dubhe-fpga" + +config SYS_TEXT_BASE + default 0x83000000 if SPL + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x80000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x80100000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select GENERIC_RISCV + select SUPPORT_SPL + select BINMAN + imply DM_SERIAL + imply SIFIVE_SERIAL + imply CMD_SF + +endif diff --git a/board/starfive/dubhe_fpga/MAINTAINERS b/board/starfive/dubhe_fpga/MAINTAINERS new file mode 100644 index 0000000000..6b2a1eec40 --- /dev/null +++ b/board/starfive/dubhe_fpga/MAINTAINERS @@ -0,0 +1,5 @@ +STARFIVE DUBHE FPGA BOARD +M: starfive +S: Maintained +F: board/starfive/dubhe_fpga/ + diff --git a/board/starfive/dubhe_fpga/Makefile b/board/starfive/dubhe_fpga/Makefile new file mode 100644 index 0000000000..75f2af2b31 --- /dev/null +++ b/board/starfive/dubhe_fpga/Makefile @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y += dubhe_fpga_spl.o +else +obj-y += dubhe_fpga.o +endif
\ No newline at end of file diff --git a/board/starfive/dubhe_fpga/dubhe_fpga.c b/board/starfive/dubhe_fpga/dubhe_fpga.c new file mode 100755 index 0000000000..110d2a00eb --- /dev/null +++ b/board/starfive/dubhe_fpga/dubhe_fpga.c @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2021 StarFive Technology Co., Ltd. */ + +int board_init(void) +{ + return 0; +}
\ No newline at end of file diff --git a/board/starfive/dubhe_fpga/dubhe_fpga_spl.c b/board/starfive/dubhe_fpga/dubhe_fpga_spl.c new file mode 100755 index 0000000000..d7a745e8c7 --- /dev/null +++ b/board/starfive/dubhe_fpga/dubhe_fpga_spl.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2021 StarFive Technology Co., Ltd. */ + +#include <spl.h> + +int spl_board_init_f(void) +{ + return 0; +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_SPI; +} + +int board_fit_config_name_match(const char *name) +{ + return 0; +} diff --git a/configs/starfive_dubhe_fpga_defconfig b/configs/starfive_dubhe_fpga_defconfig new file mode 100644 index 0000000000..a7163d9a15 --- /dev/null +++ b/configs/starfive_dubhe_fpga_defconfig @@ -0,0 +1,39 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="dubhe_fpga" +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_TARGET_STARFIVE_DUBHE_FPGA=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +# CONFIG_SPL_SMP is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttySIF0,115200 earlycon=sbi root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="echo Dubhe FPGA booting from serial flash...; sf probe 1:0; sf read 0x84000000 0x400000 0x1200000; bootm 0x84000000" +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x22000 +CONFIG_CMD_MTD=y +CONFIG_CMD_MTDPARTS=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_CLK=y +CONFIG_DM_MTD=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPI=y +CONFIG_SPI_SIFIVE=y diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4587215984..673a94964f 100644..100755 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -284,6 +284,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25uw12345g", 0xc28438, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25uw6445g", 0xc28137, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25uw6345g", 0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ diff --git a/include/configs/starfive-dubhe-fpga.h b/include/configs/starfive-dubhe-fpga.h new file mode 100644 index 0000000000..47957949b1 --- /dev/null +++ b/include/configs/starfive-dubhe-fpga.h @@ -0,0 +1,16 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SPL_MAX_SIZE 0x00200000 +#define CONFIG_SPL_BSS_START_ADDR 0x80300000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80400000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 +#define CONFIG_SPL_STACK 0x80500000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x80500000 +#define CONFIG_SYS_LOAD_ADDR 0x84000000 +#define CONFIG_SYS_MALLOC_LEN 0x00100000 +#define CONFIG_SYS_BOOTM_LEN 0x04000000 +#endif /* __CONFIG_H */ |