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authorWei Liang Lim <weiliang.lim@starfivetech.com>2023-10-21 12:28:52 +0300
committerWei Liang Lim <weiliang.lim@starfivetech.com>2023-10-21 12:28:52 +0300
commitea34117e3e60c7ab65543f9ad9e0eb3e248f5ccd (patch)
tree7b666c1fc396d5b4d33de26e0525d4db0d208d4e
parentf32bc7c99e6e4a3af417edb6791ca452fb593ca0 (diff)
downloadu-boot-ea34117e3e60c7ab65543f9ad9e0eb3e248f5ccd.tar.xz
configs: starfive_dubhe_fpga_defconfig: Enable Dubhe SMP
Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
-rw-r--r--arch/riscv/cpu/dubhe/Kconfig4
-rw-r--r--configs/starfive_dubhe_fpga_defconfig3
2 files changed, 4 insertions, 3 deletions
diff --git a/arch/riscv/cpu/dubhe/Kconfig b/arch/riscv/cpu/dubhe/Kconfig
index 7f0ce08a39..50ff1a9ca7 100644
--- a/arch/riscv/cpu/dubhe/Kconfig
+++ b/arch/riscv/cpu/dubhe/Kconfig
@@ -4,17 +4,19 @@
config STARFIVE_DUBHE
bool
+ select SUPPORT_SPL
select BINMAN if SPL
select ARCH_EARLY_INIT_R
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
imply SIFIVE_CLINT if RISCV_MMODE
- imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
+ imply SPL_RISCV_ACLINT
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT
+ imply SMP
imply MII
config SYS_CACHELINE_SIZE
diff --git a/configs/starfive_dubhe_fpga_defconfig b/configs/starfive_dubhe_fpga_defconfig
index 7cd1c06440..4e1da4885b 100644
--- a/configs/starfive_dubhe_fpga_defconfig
+++ b/configs/starfive_dubhe_fpga_defconfig
@@ -3,14 +3,12 @@ CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="dubhe_fpga"
-CONFIG_SUPPORT_SPL=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_TARGET_STARFIVE_DUBHE_FPGA=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
-# CONFIG_SPL_SMP is not set
CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
@@ -82,3 +80,4 @@ CONFIG_SPL_RAM_DEVICE=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_NR_CPUS=2