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authorWei Liang Lim <weiliang.lim@starfivetech.com>2023-10-21 05:02:26 +0300
committerWei Liang Lim <weiliang.lim@starfivetech.com>2023-10-21 05:02:26 +0300
commitf204b8c6084bc66e96d8167f5c7da87e1409fea5 (patch)
treec94af88d36180d50599880ff613ba0e87a8e18ee
parenta548724944c97b0db7ac30921815fec39d3f00db (diff)
downloadu-boot-f204b8c6084bc66e96d8167f5c7da87e1409fea5.tar.xz
arch: riscv: dts: dubhe-fpga-u-boot.dtsi: Update CPU1 node
Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
-rw-r--r--arch/riscv/dts/dubhe-fpga-u-boot.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi
index 7760d81b27..50f4f31ddf 100644
--- a/arch/riscv/dts/dubhe-fpga-u-boot.dtsi
+++ b/arch/riscv/dts/dubhe-fpga-u-boot.dtsi
@@ -15,6 +15,10 @@
cpu@0 {
bootph-all;
};
+
+ cpu@1 {
+ bootph-all;
+ };
};
memory@80000000 {