Merge branch 'CR_10259_add_amp_minda' into 'jh7110-master'HEADJH7110_VF2_6.6_v5.12.0JH7110_VF2_6.1_v5.12.0JH7110_VF2_515_v5.12.0JH7110_VisionFive2_devel

CR_10259 spl: amp: Enable UART2 and move rtos image to memory

See merge request sdk/u-boot!83

4 files changed, 124 insertions, 2 deletions

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 79679c91ad..0cbe2247fb 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,8 +7,8 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_DEVKITS) += starfive_devkits.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += starfive_visionfive2.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_DEVKITS) += starfive_devkits.dtb starfive_jh7110-amp.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += starfive_visionfive2.dtb starfive_jh7110-amp.dtb
 dtb-$(CONFIG_TARGET_STARFIVE_EVB) += starfive_evb.dtb
 
 targets += $(dtb-y)
diff --git a/arch/riscv/dts/starfive_jh7110-amp-u-boot.dtsi b/arch/riscv/dts/starfive_jh7110-amp-u-boot.dtsi
new file mode 100644
index 0000000000..e222046afa
--- /dev/null
+++ b/arch/riscv/dts/starfive_jh7110-amp-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#if defined(CONFIG_TARGET_STARFIVE_VISIONFIVE2)
+#include "starfive_visionfive2-u-boot.dtsi"
+#endif
+#if defined(CONFIG_TARGET_STARFIVE_DEVKITS)
+#include "starfive_devkits-u-boot.dtsi"
+#endif
+
+/ {
+	config {
+		amp,rtos-offset = <0x330000>;
+		amp,rtos-code-base = <0x6e800000>;
+	};
+};
diff --git a/arch/riscv/dts/starfive_jh7110-amp.dts b/arch/riscv/dts/starfive_jh7110-amp.dts
new file mode 100644
index 0000000000..2f284e7bce
--- /dev/null
+++ b/arch/riscv/dts/starfive_jh7110-amp.dts
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#if defined(CONFIG_TARGET_STARFIVE_VISIONFIVE2)
+#include "starfive_visionfive2.dts"
+#endif
+#if defined(CONFIG_TARGET_STARFIVE_DEVKITS)
+#include "starfive_devkits.dts"
+#endif
+
+/ {
+	chosen {
+		opensbi-domains {
+			compatible = "opensbi,domain,config";
+
+			rpmsg_shmem: rpmsg_shmem {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x6e400000>;
+				order = <22>;
+			};
+
+			rtcode: rtcode {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x6e800000>;
+				order = <23>;
+			};
+
+			rtheap: rtheap {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x6f000000>;
+				order = <24>;
+			};
+
+			dram0: dram0 {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x40000000>;
+				order = <30>;
+			};
+
+			dram1: dram1 {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x80000000>;
+				order = <31>;
+			};
+
+			allmem: allmem {
+				compatible = "opensbi,domain,memregion";
+				base = <0x0 0x0>;
+				order = <64>;
+			};
+
+			udomain: u-domain {
+				compatible = "opensbi,domain,instance";
+				possible-harts = <&cpu0 &cpu1 &cpu2 &cpu3>;
+				regions = <&rtcode 0x0>, <&rtheap 0x0>, <&allmem 0x3f>;
+				next-addr = <0x0 0x40200000>;
+				boot-hart = <&cpu1>;
+				system-reset-allowed;
+				system-suspend-allowed;
+			};
+
+			rtdomain: rt-domain {
+				compatible = "opensbi,domain,instance";
+				possible-harts = <&cpu4>;
+				regions = <&rpmsg_shmem 0x3f>, <&rtcode 0x3f>, <&rtheap 0x3f>,
+					<&dram1 0x0>, <&allmem 0x3f>;
+				boot-hart = <&cpu4>;
+				next-arg1 = <0x0 0x0>;
+				next-addr = <0x0 0x6e800000>;
+				next-mode = <0x1>;
+			};
+		};
+	};
+};
+
+&cpu0 {
+	opensbi-domain = <&udomain>;
+};
+
+&cpu1 {
+	opensbi-domain = <&udomain>;
+};
+
+&cpu2 {
+	opensbi-domain = <&udomain>;
+};
+
+&cpu3 {
+	opensbi-domain = <&udomain>;
+};
+
+&cpu4 {
+	opensbi-domain = <&rtdomain>;
+};
+
+&gmac1 {
+	status = "disabled";
+};
diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
index 156709e6ae..03a7293985 100644
--- a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
+++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
@@ -114,5 +114,8 @@
 #define CLK_QSPI_REF_SW_SHIFT	24
 #define CLK_QSPI_REF_SW_MASK	0x1000000U
 
+#define CLK_UART2_APB_OFFSET   0x254
+#define CLK_UART2_CORE_OFFSET  0x258
+#define CLK_RSTN_3_OFFSET      0x300
 #endif /* __STARFIVE_JH7110_REGS_H */