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| author | Samin Guo <samin.guo@starfivetech.com> | 2022-11-01 13:52:31 +0300 |
|---|---|---|
| committer | Samin Guo <samin.guo@starfivetech.com> | 2022-11-02 07:45:48 +0300 |
| commit | bf2eae30d4aa6312e5a8578b12e8c3aa66a93fb0 (patch) | |
| tree | d97b9afa536d5f15568f7ac13c22040f5ba7eac1 /board | |
| parent | 945a1c00275fa1e81678dfa54d430f0877cd8146 (diff) | |
| download | u-boot-bf2eae30d4aa6312e5a8578b12e8c3aa66a93fb0.tar.xz | |
driver:qspi: Switch the QSPI parent clock to pll0
Switch the QSPI parent clock to pll0 to improve the QSPI speed
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/starfive/evb/spl.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/board/starfive/evb/spl.c b/board/starfive/evb/spl.c index b55efa1e81..8cab704031 100644 --- a/board/starfive/evb/spl.c +++ b/board/starfive/evb/spl.c @@ -89,7 +89,10 @@ void board_init_f(ulong dummy) CLK_AON_APB_FUNC_SW_MASK, BIT(CLK_AON_APB_FUNC_SW_SHIFT) & CLK_AON_APB_FUNC_SW_MASK); - + /* switch qspi clk to pll0 */ + clrsetbits_le32(SYS_CRG_BASE + CLK_QSPI_REF_OFFSET, + CLK_QSPI_REF_SW_MASK, + BIT(CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK); /*set GPIO to 1.8v*/ setbits_le32(SYS_SYSCON_BASE + 0xC, 0xf); |