diff options
| author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-04-26 12:22:34 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:34 +0300 |
| commit | f95a5cec9fd49737ce570098be96d0c4d5c40ea8 (patch) | |
| tree | 43f44d10017278a23e1a16948fc9ca151bea7b91 /board | |
| parent | 3d8b5aeca1e41c1a5632e242db45a59b9a439a04 (diff) | |
| download | u-boot-f95a5cec9fd49737ce570098be96d0c4d5c40ea8.tar.xz | |
board:starfive: add rtc timer init
The rtc timer is used early in kernel, but the clk&reset driver is not
ready,so some clk&reset init is placed here.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'board')
| -rwxr-xr-x[-rw-r--r--] | board/starfive/visionfive/starfive_visionfive.c | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/board/starfive/visionfive/starfive_visionfive.c b/board/starfive/visionfive/starfive_visionfive.c index 6a8f8319a0..7f9de3d9de 100644..100755 --- a/board/starfive/visionfive/starfive_visionfive.c +++ b/board/starfive/visionfive/starfive_visionfive.c @@ -37,6 +37,39 @@ SYS_IOMUX_DOUT(gpio, gpo);\ SYS_IOMUX_DIN(gpio, gpi); }while(0) +#define SYS_CLOCK_ENABLE(clk) \ + setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK) + +static void sys_reset_clear(ulong assert, ulong status, u32 rst) +{ + volatile u32 value; + + clrbits_le32(SYS_CRG_BASE + assert, BIT(rst)); + do{ + value = in_le32(SYS_CRG_BASE + status); + }while((value & BIT(rst)) != BIT(rst)); +} + +static void jh7110_timer_init(void) +{ + SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT); + SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT); + SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT); + SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT); + SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT); + + sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, + SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT); + sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, + SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT); + sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, + SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT); + sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, + SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT); + sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT, + SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT); +} + static void jh7110_gmac_init(int id) { switch (id) { @@ -129,6 +162,8 @@ int board_init(void) jh7110_gmac_init(0); jh7110_gmac_init(1); + jh7110_timer_init(); + jh7110_usb_init(); jh7110_mmc_init(0); @@ -160,7 +195,8 @@ int misc_init_r(void) if (ret) printf("%s: error reading mac from OTP\n", __func__); else - memcpy(mac, buf, 6); + if (buf[0] != 0xff) + memcpy(mac, buf, 6); err: #endif eth_env_set_enetaddr("ethaddr", mac); |