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2021-12-28Merge tag 'video-20211228' of ↵masterTom Rini1-2/+2
https://source.denx.de/u-boot/custodians/u-boot-video - mxsfb axi/disp_axi clock enable fix
2021-12-28Merge tag 'efi-2022-01-rc4-4' of ↵Tom Rini9-18/+29
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2022-01-rc4-4 UEFI: * allow for more than 16 KiB UEFI variable size when using StMM Others: * make watchdog sysreset compatible with separate poweroff driver * avoid OpenSSL deprecation warnings
2021-12-27doc: Fix usage of CFG_RPMB_WRITE_KEYIlias Apalodimas1-3/+3
This is a 'y/n' selection, so fix it. While at it remove the duplicate usage of CFG_CORE_HEAP_SIZE Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-27video: mxsfb: fix clk_get_by_name() return value checkGiulio Benetti1-2/+2
If clk_get_by_name() returns 0 it means it executed successfully while now we consider it as an error. So let's check if return value is negative to be an error. Otherwise this prevents "axi" and "disp_axi" to be enabled. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-12-26Merge https://source.denx.de/u-boot/custodians/u-boot-spiTom Rini3-6/+22
2021-12-26Merge tag 'u-boot-rockchip-20211226' of ↵Tom Rini36-374/+1225
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add kaslrseed support; - rk3568 spl and image tool support; - px30 dts sync from kernel; - rk3399 emmc fix; - rockchip fastboot cmd fix;
2021-12-26tools: avoid OpenSSL deprecation warningsHeinrich Schuchardt4-0/+9
Our Gitlab CI buildsystem is set up to treat warnings as errors. With OpenSSL 3.0 a lot of deprecation warnings occur. With the patch compatibility with OpenSSL 1.1.1 is declared. In the long run we should upgrade our code to use the current API. A -Wdiscarded-qualifiers warning is muted by casting. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-26sysreset: watchdog: watchdog cannot power offHeinrich Schuchardt1-3/+10
The watchdog system reset driver can reboot the device but it cannot power it off. If power off is requested, the driver should not reset the system but leave powering off to one of the other system reset drivers. As power cycling is typically not a feature of a watchdog driver the reset types SYSRESET_POWER and SYSRESET_POWER_OFF shall both be excluded. Fixes: 17a0c14164dc ("dm: sysreset: add watchdog-reboot driver") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-26efi_loader: Don't limit the StMM buffer size explicitlyIlias Apalodimas2-11/+6
Currently we allow and explicitly check a single shared page with StandAloneMM. This is dictated by OP-TEE which runs the application. However there's no way for us dynamically discover the number of pages we are allowed to use. Since writing big EFI signature list variable requires more than a page, OP-TEE has bumped the number of shared pages to four. Let's remove our explicit check and allow the request to reach OP-TEE even if it's bigger than what it supports. There's no need to sanitize the number of pages internally. OP-TEE will fail if we try to write more than it's allowed. The error will just trigger later on, during the StMM access. While at it add an error message to help users figure out what failed. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Signed-off-by: Ilias Apalodimas <apalos@gmail.com>
2021-12-26efi: fix typo in description of struct efi_entry_hdrHeinrich Schuchardt1-1/+1
Add missing colon. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-24rockchip: mkimage: Add support for rk3568 SoCKever Yang1-0/+1
rk3568 is the first SoC which supports idb header v2. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24rockchip: mkimage: Add support for idb header V2Yi Liu1-28/+158
Rockchip BootRom supports new idb header v2 instead of legacy version. Add support for it so that we can generate image for new SoCs. Signed-off-by: Yi Liu <liuyi@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24rockchip: mkimage: Add image header versionKever Yang1-12/+17
We are going to have more than one version header, add the version in the header info. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24rockchip: mkimage: rename RK_SIGNATURE to RK_MAGICKever Yang1-5/+5
The first 4byte of idbimage is a magic number instead of signature, correct it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24configs: rock-pi-4: Enable rockchip efuse supportSjoerd Simons2-0/+2
Enable efuse support for reading the cpuid#, serial# and generate a board unique mac address Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24rockchip: boot_mode: fix fastboot commandJohn Keeping1-1/+1
The USB controller index must be separated from the type argument, otherwise the preboot command fails with the error: Error: Wrong USB controller index format Add the missing space to fix fastboot mode here. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24power: pmic/fan53555: allow dm be omitted by SPLQuentin Schulz2-1/+15
Allow the dm driver be omitted by SPL. Cc: Quentin Schulz <foss+u-boot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24engicam: px30: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OFJagan Teki4-0/+123
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24arm64: dts: rockchip: Sync px30 from linux-nextJagan Teki16-255/+681
Sync the px30 devicetree files from linux-next tree. commit <14ce8069f48b> ("lib/stackdepot: allow optional init and stack_table allocation by kvmalloc() - fixup3") Note, this path even sync rk3326 files as it depends on px30. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsiJagan Teki3-13/+12
dmc node is specific to U-Boot, it is always better practice to maintain U-Boot specific nodes into -u-boot.dtsi files in order to maintain Linux dts file sync compatibility. Move the dmc into px30-u-boot.dtsi, also add dmc node explicitly in rk3326-odroid-go2-u-boot.dtsi since it is using px30.dts. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24doc: rockchip: puma: update build and flash instructionsQuentin Schulz2-55/+38
Long gone is the time a custom TF-A was needed for Puma, upstream TF-A works just fine now. The flashing instructions are updated to match how newer rkdeveloptool and rkbin work. Finally, rkbin provides a way to flash SPI via USB OTG interface so let's document that. Cc: Quentin Schulz <foss+u-boot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24dts: rockchip: rk3399: enable emmc phy for splYifeng Zhao1-0/+4
adapting commit ac804143cf ("mmc: rockchip_sdhci: add phy and clock config for rk3399") to fix the issue "Not found emmc phy device". Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> - on a Rock960 Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se> - on a Pinebook Pro Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24rockchip: rk3568: add arch_cpu_init()Nico Cheng1-3/+24
We configured the drive strength and security of EMMC in arch_cpu_init(). Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24arm: dts: rockchip: rk3568: Enable sdhci and sdmmc0 nodeNico Cheng1-0/+17
Enable sdhci and sdmmc0 node in rk3568-u-boot.dtsi Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24rockchip: Kconfig: Enable SPL support for rk3568Nico Cheng3-1/+32
Enable SPL support in Kconfig and add some related option in rk3568_common.h Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com> Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24rockchip: px30: add support for HW RNG for Odroid Go AdvanceChris Morgan1-0/+6
The Odroid Go Advance has a hardware random number generator present. The device does not have an upstream Linux driver, but does have a U-Boot driver. Add the appropriate node so that the hardware RNG can be used in U-Boot. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24cmd: kaslrseed: add command to generate value from hwrngChris Morgan3-0/+89
Allow the kaslr-seed value in the chosen node to be set from a hardware rng source. Tested on a Rockchip PX30 (Odroid Go Advance), you must have loaded the devicetree first and prepared it for editing. On my device the workflow goes as follows: setenv dtb_loadaddr "0x01f00000" load mmc 0:1 ${dtb_loadaddr} rk3326-odroid-go2.dtb fdt addr ${dtb_loadaddr} fdt resize kaslrseed and the output can be seen here: fdt print /chosen chosen { kaslr-seed = <0x6f61df74 0x6f7b996c>; stdout-path = "serial2:115200n8"; }; Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-20Prepare v2022.01-rc4Tom Rini1-1/+1
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-20Revert "image: Remove #ifdefs from select_ramdisk()"Tom Rini1-72/+67
This reverts commit f33a2c1bd0fb371511a485cac1f182ba50db51be. This causes a crash on some platforms as seen here: https://lore.kernel.org/r/f153017b-c41a-0d32-67b9-f288e695f900@baylibre.com/ Reported-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-20fw_setenv: Unbreak fw_setenv caused by buggy MEMISLOCKED useJoakim Tjernlund1-7/+8
Commit "fw_setenv: lock the flash only if it was locked before" checks for Locked status with uninitialized erase data. Address by moving the test for MEMISLOCKED. Fixes: 8a726b852502 ("fw_setenv: lock the flash only if it was locked before") Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
2021-12-20Merge tag '20211220-fixes-for-2022.01' of ↵Tom Rini1-2/+10
https://source.denx.de/u-boot/custodians/u-boot-i2c i2c changes for 20211220-fixes-for-2022.01 - mvtwsi: Swab the register address if its size is > 1
2021-12-20i2c: mvtwsi: Swab the register address if its size is > 1Stefan Roese1-2/+10
Testing on Armada XP with an EEPROM using register address with size of 2 has shown, that the register address bytes are sent to the I2C EEPROM in the incorrect order. This patch swabs the address bytes so that the correct address is transferred to the I2C device. BTW: This worked without any issues before migrating Armada XP to DM I2C. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Samuel Holland <samuel@sholland.org> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Pali Rohár <pali@kernel.org> Cc: Marek Behún <marek.behun@nic.cz> Tested-by: Marek Behún <marek.behun@nic.cz>
2021-12-18Merge tag 'efi-2022-01-rc4-3' of ↵Tom Rini7-5/+119
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2022-01-rc4-3 Documentation: * add Calxeda Highbank/Midway board documentation Bug fixes: * call part_init() in blk_get_device_by_str() only for MMC * fix an 'undefined' error in some driver model macros
2021-12-18dm: fix an 'undefined' error in some macrosAKASHI Takahiro1-4/+4
Due to a non-existing parameter name in macro's, use of those macro's will cause a compiler error of "undefined reference". Unfortunately, dm test doesn't fail because a wrong name ("&dev", hence it is accidentally a valid name in the context of a caller site) is passed on. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Fixes: f262d4ca4b2b ("dm: core: Add a way to read platdata for all child devices") Fixes: 903e83ee8464 ("dm: core: Add a way to iterate through children, probing each") Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-18blk: add a helper function, blk_probe_or_unbind()AKASHI Takahiro2-0/+25
This function will be commonly used in block device drivers in the succeeding patches. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-18part: call part_init() in blk_get_device_by_str() only for MMCAKASHI Takahiro1-1/+2
In blk_get_device_by_str(), the comment says: "Updates the partition table for the specified hw partition." Since hw partition is supported only on MMC, it makes no sense to do so for other devices. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-18doc: board: Add Calxeda Highbank/Midway documentationAndre Przywara3-0/+88
The Calxeda servers are using U-Boot as the primary bootloader, which was shipped as part of a firmware upgrade package. Even though the machines are considered legacy at this point, the port still works, so deserves some documentation. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-17Merge commit '4720b83d2c711062cfb55f03591b8f12c897d7cb' of ↵Tom Rini6-9/+260
https://github.com/tienfong/uboot_mainline
2021-12-17arm: socfpga: arria10: Enable double peripheral RBF configurationTien Fong Chee4-1/+54
Double peripheral RBF configuration are needed on some devices or boards to stabilize the IO configuration system. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBFTien Fong Chee5-6/+195
This patch triggers warm reset to recover the MPFE NoC from corruption due to high frequency transient clock output from HPS EMIF IOPLL at VCO startup after peripheral RBF is programmed. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17arm: socfpga: arria10: Setting image magic value to romcode initswstate regTien Fong Chee2-2/+11
The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID value if the current FSBL image is found valid, otherwise BootROM will look for next subsequent valid FSBL image when warm reset is triggered. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-16mtd: spi-nor-ids: Add support for W25Q01JVRam Narayanan1-0/+5
Adds support for Winbond's new 128MB spi nor flash. datasheet: https://www.winbond.com/resource-files/W25Q01JV%20SPI%20RevC%2005032021%20Plus%20dummy.pdf Signed-off-by: Ram Narayanan <ramnara@linux.microsoft.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-12-15Merge tag 'clk-2022.01-rc3' of ↵Tom Rini10-28/+59
https://source.denx.de/u-boot/custodians/u-boot-clk Clock patches for v2022.01-rc3 This adds better logging support for many CCF drivers, and clarifies some documentation regarding clk_get_rate.
2021-12-15clk: define LOG_CATEGORY for generic and ccf clocksPatrick Delaunay8-12/+39
Define LOG_CATEGORY to allow filtering with log command for generic clock and CCF clocks. This patch also change existing printf, debug and pr_ macro to log_ or dev_ macro. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-12-15clk: cosmetic: reorder include filesPatrick Delaunay6-15/+18
Reorder include files in the U-Boot expected order: the common.h header should always be first, followed by other headers in order, then headers with directories, then local files. It is a preliminary step for next patch. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-12-15clk: fix clk_get_rate() documentationGiulio Benetti1-1/+2
Improve clk_get_rate() @return documentation that otherwise is a bit ambiguous. At the moment I expect to return 0 as error since the return type is 'ulong', instead the function really returns negative value in case the corresponding function pointer is null and returns 0 if the clock is invalid. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-12-15Merge tag 'rpi-next-2022.01' of ↵Tom Rini2-2/+8
https://source.denx.de/u-boot/custodians/u-boot-raspberrypi - enable RPi Zero 2 W - fix MMC numbering issue - Update link to documentation
2021-12-15Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini2-48/+61
- Marvell/PCI: Fix size of the configuration cache and disallow ROM BAR setting in pci_mvebu.c & pci-aardvark.c (Pali & Marek)
2021-12-15arm: a37xx: pci: Do not allow setting ROM BAR on PCI BridgePali Rohár1-24/+30
PCI Bridge which represents aardvark PCIe Root Port has Expansion ROM Base Address register at offset 0x30 but its meaning is different than PCI's Expansion ROM BAR register. Only address format of register is same. In reality, this device does not have any configurable PCI BARs. So ensure that write operation into BARs (including Expansion ROM BAR) is noop and registers always contain zero address which indicates that bars are unsupported. Fixes: cb056005dc67 ("arm: a37xx: pci: Add support for accessing PCI Bridge on root bus") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-15pci: pci_mvebu: Do not allow setting ROM BAR on PCI BridgePali Rohár1-24/+31
The PCI Bridge which represents mvebu PCIe Root Port has Expansion ROM Base Address register at offset 0x30 but its meaning is different that of PCI's Expansion ROM BAR register, although the address format of the register is the same. In reality, this device does not have any configurable PCI BARs. So ensure that write operation into BARs (including Expansion ROM BAR) is a noop and registers always contain zero address which indicates that BARs are unsupported. Fixes: a7b61ab58d5d ("pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
generated by cgit v1.2.3 (git 2.39.0) at 2024-06-02 15:11:56 +0300