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| author | Lei YU <mine260309@gmail.com> | 2017-03-01 06:29:50 +0300 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2017-03-02 06:36:29 +0300 |
| commit | bdcc0d7f61c5e15086dbfc1bfae11946ce6c11ea (patch) | |
| tree | b4a4fb86986fb466a763d13b30e1f4ef5593e467 | |
| parent | 39eb5a44bfd49fe530f6b68c4d99ab2d8d391be0 (diff) | |
| download | linux-bdcc0d7f61c5e15086dbfc1bfae11946ce6c11ea.tar.xz | |
arm: aspeed: romulus: Set PNOR SPI address mapping
The PNOR SPI address mapping is the same as Witherspoon.
Even though Romulus only has the one flash chip we want to map (on CE0),
we need to move the CE1 mapping/window out of the way or else the
controller is unhappy.
The upstream aspeed smc driver will gain support for setting these
registers in the future so we can drop these hacks.
Signed-off-by: Lei YU <mine260309@gmail.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
[Joel: add some content to the commit message]
Signed-off-by: Joel Stanley <joel@jms.id.au>
| -rw-r--r-- | arch/arm/mach-aspeed/aspeed.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c index 726b8fa96dda..7ac006aaa5f4 100644 --- a/arch/arm/mach-aspeed/aspeed.c +++ b/arch/arm/mach-aspeed/aspeed.c @@ -221,6 +221,12 @@ static void __init do_witherspoon_setup(void) static void __init do_romulus_setup(void) { do_common_setup(); + + /* Set SPI1 CE1 decoding window to 0x34000000 */ + writel(0x70680000, AST_IO(AST_BASE_SPI | 0x34)); + + /* Set SPI1 CE0 decoding window to 0x30000000 */ + writel(0x68600000, AST_IO(AST_BASE_SPI | 0x30)); } #define SCU_PASSWORD 0x1688A8A8 |