Update I3C bus device list

To support communication with NVDIMM controllers, add definitions for
these I3C devices. Each bus now has two definitions for each DIMM slot.
If populated with a DDR5 DIMM, the SPD Hub device will be used to gather
temperature readings. If populated with an NVDIMM, we'll only need to
talk to the controller sitting behind the hub (local device type 1011b),
to read temperature and use the FW mailbox.

This also removes some logic in the I3C driver which restricts use of
certain addresses due to signal integrity paranoia. An NVDIMM controller
in slot 6 of any bus is blocked by this logic, and unfortunately we
don't have any control over the static address scheme used on the SPD
bus, so the restriction must be removed.

Tested:
Probed I3C busses successfully with DIMMs installed in busses 0 and 1:

$ gpioset $(gpiofind FM_SPD_SWITCH_CTRL_N)=1
$ echo 1e7a2000.i3c0 > /sys/bus/platform/drivers/dw-i3c-master/bind
$ echo 1e7a3000.i3c1 > /sys/bus/platform/drivers/dw-i3c-master/bind
$ ls /dev/i3c*
/dev/i3c-0-3c000000000 /dev/i3c-0-3c000000001 /dev/i3c-0-3c000000002
/dev/i3c-0-3c000000003 /dev/i3c-0-3c000000004 /dev/i3c-0-3c000000005
/dev/i3c-0-3c000000006 /dev/i3c-0-3c000000007 /dev/i3c-0-3c000000008
/dev/i3c-0-3c000000009 /dev/i3c-0-3c00000000a /dev/i3c-0-3c00000000b
/dev/i3c-0-3c00000000c /dev/i3c-0-3c00000000d /dev/i3c-0-3c00000000e
/dev/i3c-1-3c000000000 /dev/i3c-1-3c000000001 /dev/i3c-1-3c000000002
/dev/i3c-1-3c000000003 /dev/i3c-1-3c000000004 /dev/i3c-1-3c000000005
/dev/i3c-1-3c000000006 /dev/i3c-1-3c000000007 /dev/i3c-1-3c000000008
/dev/i3c-1-3c000000009 /dev/i3c-1-3c00000000a /dev/i3c-1-3c00000000b
/dev/i3c-1-3c00000000c /dev/i3c-1-3c00000000d /dev/i3c-1-3c00000000e

Change-Id: I016450edad1ed4ec981500f04122976f1647b8ee
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

2 files changed, 168 insertions, 1 deletions

diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
index 03a9e757b527..872a25579644 100644
--- a/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
@@ -499,47 +499,87 @@
 		assigned-address = <0x50>;
 	};
 
+	nvdimm_0_0: nvm@58,3C0000000008 {
+		reg = <0x58 0x3C0 0x00000008>;
+		assigned-address = <0x58>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_0_1: spd@51,3C000000001 {
 		reg = <0x51 0x3C0 0x00000001>;
 		assigned-address = <0x51>;
 	};
 
+	nvdimm_0_1: nvm@59,3C0000000009 {
+		reg = <0x59 0x3C0 0x00000009>;
+		assigned-address = <0x59>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_0_2: spd@52,3C000000002 {
 		reg = <0x52 0x3C0 0x00000002>;
 		assigned-address = <0x52>;
 	};
 
+	nvdimm_0_2: nvm@5A,3C000000000A {
+		reg = <0x5A 0x3C0 0x0000000A>;
+		assigned-address = <0x5A>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_0_3: spd@53,3C000000003 {
 		reg = <0x53 0x3C0 0x00000003>;
 		assigned-address = <0x53>;
 	};
 
+	nvdimm_0_3: nvm@5B,3C000000000B {
+		reg = <0x5B 0x3C0 0x0000000B>;
+		assigned-address = <0x5B>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_0_4: spd@54,3C000000004 {
 		reg = <0x54 0x3C0 0x00000004>;
 		assigned-address = <0x54>;
 	};
 
+	nvdimm_0_4: nvm@5C,3C000000000C {
+		reg = <0x5C 0x3C0 0x0000000C>;
+		assigned-address = <0x5C>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_0_5: spd@55,3C000000005 {
 		reg = <0x55 0x3C0 0x00000005>;
 		assigned-address = <0x55>;
 	};
 
+	nvdimm_0_5: nvm@5D,3C000000000D {
+		reg = <0x5D 0x3C0 0x0000000D>;
+		assigned-address = <0x5D>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_0_6: spd@56,3C000000006 {
 		reg = <0x56 0x3C0 0x00000006>;
 		assigned-address = <0x56>;
 	};
 
+	nvdimm_0_6: nvm@5E,3C000000000E {
+		reg = <0x5E 0x3C0 0x0000000E>;
+		assigned-address = <0x5E>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_0_7: spd@57,3C000000007 {
 		reg = <0x57 0x3C0 0x00000007>;
 		assigned-address = <0x57>;
 	};
+
+	nvdimm_0_7: nvm@5F,3C000000000F {
+		reg = <0x5F 0x3C0 0x0000000F>;
+		assigned-address = <0x5F>;
+	};
 };
 
 &i3c1 {
@@ -553,47 +593,87 @@
 		assigned-address = <0x50>;
 	};
 
+	nvdimm_1_0: nvm@58,3C0000000008 {
+		reg = <0x58 0x3C0 0x00000008>;
+		assigned-address = <0x58>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_1_1: spd@51,3C000000001 {
 		reg = <0x51 0x3C0 0x00000001>;
 		assigned-address = <0x51>;
 	};
 
+	nvdimm_1_1: nvm@59,3C0000000009 {
+		reg = <0x59 0x3C0 0x00000009>;
+		assigned-address = <0x59>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_1_2: spd@52,3C000000002 {
 		reg = <0x52 0x3C0 0x00000002>;
 		assigned-address = <0x52>;
 	};
 
+	nvdimm_1_2: nvm@5A,3C000000000A {
+		reg = <0x5A 0x3C0 0x0000000A>;
+		assigned-address = <0x5A>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_1_3: spd@53,3C000000003 {
 		reg = <0x53 0x3C0 0x00000003>;
 		assigned-address = <0x53>;
 	};
 
+	nvdimm_1_3: nvm@5B,3C000000000B {
+		reg = <0x5B 0x3C0 0x0000000B>;
+		assigned-address = <0x5B>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_1_4: spd@54,3C000000004 {
 		reg = <0x54 0x3C0 0x00000004>;
 		assigned-address = <0x54>;
 	};
 
+	nvdimm_1_4: nvm@5C,3C000000000C {
+		reg = <0x5C 0x3C0 0x0000000C>;
+		assigned-address = <0x5C>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_1_5: spd@55,3C000000005 {
 		reg = <0x55 0x3C0 0x00000005>;
 		assigned-address = <0x55>;
 	};
 
+	nvdimm_1_5: nvm@5D,3C000000000D {
+		reg = <0x5D 0x3C0 0x0000000D>;
+		assigned-address = <0x5D>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_1_6: spd@56,3C000000006 {
 		reg = <0x56 0x3C0 0x00000006>;
 		assigned-address = <0x56>;
 	};
 
+	nvdimm_1_6: nvm@5E,3C000000000E {
+		reg = <0x5E 0x3C0 0x0000000E>;
+		assigned-address = <0x5E>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_1_7: spd@57,3C000000007 {
 		reg = <0x57 0x3C0 0x00000007>;
 		assigned-address = <0x57>;
 	};
+
+	nvdimm_1_7: nvm@5F,3C000000000F {
+		reg = <0x5F 0x3C0 0x0000000F>;
+		assigned-address = <0x5F>;
+	};
 };
 
 &i3c2 {
@@ -607,47 +687,87 @@
 		assigned-address = <0x50>;
 	};
 
+	nvdimm_2_0: nvm@58,3C0000000008 {
+		reg = <0x58 0x3C0 0x00000008>;
+		assigned-address = <0x58>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_2_1: spd@51,3C000000001 {
 		reg = <0x51 0x3C0 0x00000001>;
 		assigned-address = <0x51>;
 	};
 
+	nvdimm_2_1: nvm@59,3C0000000009 {
+		reg = <0x59 0x3C0 0x00000009>;
+		assigned-address = <0x59>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_2_2: spd@52,3C000000002 {
 		reg = <0x52 0x3C0 0x00000002>;
 		assigned-address = <0x52>;
 	};
 
+	nvdimm_2_2: nvm@5A,3C000000000A {
+		reg = <0x5A 0x3C0 0x0000000A>;
+		assigned-address = <0x5A>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_2_3: spd@53,3C000000003 {
 		reg = <0x53 0x3C0 0x00000003>;
 		assigned-address = <0x53>;
 	};
 
+	nvdimm_2_3: nvm@5B,3C000000000B {
+		reg = <0x5B 0x3C0 0x0000000B>;
+		assigned-address = <0x5B>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_2_4: spd@54,3C000000004 {
 		reg = <0x54 0x3C0 0x00000004>;
 		assigned-address = <0x54>;
 	};
 
+	nvdimm_2_4: nvm@5C,3C000000000C {
+		reg = <0x5C 0x3C0 0x0000000C>;
+		assigned-address = <0x5C>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_2_5: spd@55,3C000000005 {
 		reg = <0x55 0x3C0 0x00000005>;
 		assigned-address = <0x55>;
 	};
 
+	nvdimm_2_5: nvm@5D,3C000000000D {
+		reg = <0x5D 0x3C0 0x0000000D>;
+		assigned-address = <0x5D>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_2_6: spd@56,3C000000006 {
 		reg = <0x56 0x3C0 0x00000006>;
 		assigned-address = <0x56>;
 	};
 
+	nvdimm_2_6: nvm@5E,3C000000000E {
+		reg = <0x5E 0x3C0 0x0000000E>;
+		assigned-address = <0x5E>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_2_7: spd@57,3C000000007 {
 		reg = <0x57 0x3C0 0x00000007>;
 		assigned-address = <0x57>;
 	};
+
+	nvdimm_2_7: nvm@5F,3C000000000F {
+		reg = <0x5F 0x3C0 0x0000000F>;
+		assigned-address = <0x5F>;
+	};
 };
 
 &i3c3 {
@@ -661,47 +781,87 @@
 		assigned-address = <0x50>;
 	};
 
+	nvdimm_3_0: nvm@58,3C0000000008 {
+		reg = <0x58 0x3C0 0x00000008>;
+		assigned-address = <0x58>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_3_1: spd@51,3C000000001 {
 		reg = <0x51 0x3C0 0x00000001>;
 		assigned-address = <0x51>;
 	};
 
+	nvdimm_3_1: nvm@59,3C0000000009 {
+		reg = <0x59 0x3C0 0x00000009>;
+		assigned-address = <0x59>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_3_2: spd@52,3C000000002 {
 		reg = <0x52 0x3C0 0x00000002>;
 		assigned-address = <0x52>;
 	};
 
+	nvdimm_3_2: nvm@5A,3C000000000A {
+		reg = <0x5A 0x3C0 0x0000000A>;
+		assigned-address = <0x5A>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_3_3: spd@53,3C000000003 {
 		reg = <0x53 0x3C0 0x00000003>;
 		assigned-address = <0x53>;
 	};
 
+	nvdimm_3_3: nvm@5B,3C000000000B {
+		reg = <0x5B 0x3C0 0x0000000B>;
+		assigned-address = <0x5B>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_3_4: spd@54,3C000000004 {
 		reg = <0x54 0x3C0 0x00000004>;
 		assigned-address = <0x54>;
 	};
 
+	nvdimm_3_4: nvm@5C,3C000000000C {
+		reg = <0x5C 0x3C0 0x0000000C>;
+		assigned-address = <0x5C>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_3_5: spd@55,3C000000005 {
 		reg = <0x55 0x3C0 0x00000005>;
 		assigned-address = <0x55>;
 	};
 
+	nvdimm_3_5: nvm@5D,3C000000000D {
+		reg = <0x5D 0x3C0 0x0000000D>;
+		assigned-address = <0x5D>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_3_6: spd@56,3C000000006 {
 		reg = <0x56 0x3C0 0x00000006>;
 		assigned-address = <0x56>;
 	};
 
+	nvdimm_3_6: nvm@5E,3C000000000E {
+		reg = <0x5E 0x3C0 0x0000000E>;
+		assigned-address = <0x5E>;
+	};
+
 	/* Renesas SPD5118 */
 	spd5118_3_7: spd@57,3C000000007 {
 		reg = <0x57 0x3C0 0x00000007>;
 		assigned-address = <0x57>;
 	};
+
+	nvdimm_3_7: nvm@5F,3C000000000F {
+		reg = <0x5F 0x3C0 0x0000000F>;
+		assigned-address = <0x5F>;
+	};
 };
 
 &pcieh {
diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
index a08d052f9580..05415fbc117d 100644
--- a/drivers/i3c/master.c
+++ b/drivers/i3c/master.c
@@ -2169,7 +2169,7 @@ static int of_populate_i3c_bus(struct i3c_master_controller *master)
 	struct device *dev = &master->dev;
 	struct device_node *i3cbus_np = dev->of_node;
 	struct device_node *node;
-	int ret;
+	int ret, i;
 	u32 val;
 
 	if (!i3cbus_np)
@@ -2178,6 +2178,13 @@ static int of_populate_i3c_bus(struct i3c_master_controller *master)
 	if (of_get_property(i3cbus_np, "jdec-spd", NULL))
 		master->jdec_spd = 1;
 
+	/* For SPD bus, undo unnecessary address reservations. */
+	if (master->jdec_spd) {
+		for (i = 0; i < 7; i++)
+			i3c_bus_set_addr_slot_status(&master->bus, I3C_BROADCAST_ADDR ^ BIT(i),
+						     I3C_ADDR_SLOT_FREE);
+	}
+
 	for_each_available_child_of_node(i3cbus_np, node) {
 		ret = of_i3c_master_add_dev(master, node);
 		if (ret) {