diff options
author | Vladimir Murzin <vladimir.murzin@arm.com> | 2016-11-02 14:54:06 +0300 |
---|---|---|
committer | Marc Zyngier <marc.zyngier@arm.com> | 2016-11-29 12:14:48 +0300 |
commit | 0968a61918a9140d39959a318f796412354ec24d (patch) | |
tree | a1283ec6f25af67f03d48913cc9d3be99ce3ec65 | |
parent | 328191c05ed72762c382bdb835607dd5bd56b0bc (diff) | |
download | linux-0968a61918a9140d39959a318f796412354ec24d.tar.xz |
irqchip/gic-v3-its: Specialise readq and writeq accesses
readq and writeq type of assessors are not supported in AArch32, so we
need to specialise them and glue later with series of 32-bit accesses
on AArch32 side.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
-rw-r--r-- | arch/arm64/include/asm/arch_gicv3.h | 14 | ||||
-rw-r--r-- | drivers/irqchip/irq-gic-v3-its.c | 24 |
2 files changed, 26 insertions, 12 deletions
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 546f92b32b62..f37e3a21f6e7 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -174,5 +174,19 @@ static inline void gic_write_bpr1(u32 val) #define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l)) +#define gits_read_baser(c) readq_relaxed(c) +#define gits_write_baser(v, c) writeq_relaxed(v, c) + +#define gits_read_cbaser(c) readq_relaxed(c) +#define gits_write_cbaser(v, c) writeq_relaxed(v, c) + +#define gits_write_cwriter(v, c) writeq_relaxed(v, c) + +#define gicr_read_propbaser(c) readq_relaxed(c) +#define gicr_write_propbaser(v, c) writeq_relaxed(v, c) + +#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c) +#define gicr_read_pendbaser(c) readq_relaxed(c) + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_GICV3_H */ diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index b2a6e7b0bf9a..69b040f47d56 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -835,7 +835,7 @@ static u64 its_read_baser(struct its_node *its, struct its_baser *baser) { u32 idx = baser - its->tables; - return readq_relaxed(its->base + GITS_BASER + (idx << 3)); + return gits_read_baser(its->base + GITS_BASER + (idx << 3)); } static void its_write_baser(struct its_node *its, struct its_baser *baser, @@ -843,7 +843,7 @@ static void its_write_baser(struct its_node *its, struct its_baser *baser, { u32 idx = baser - its->tables; - writeq_relaxed(val, its->base + GITS_BASER + (idx << 3)); + gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); baser->val = its_read_baser(its, baser); } @@ -1125,8 +1125,8 @@ static void its_cpu_init_lpis(void) GICR_PROPBASER_WaWb | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); - writeq_relaxed(val, rbase + GICR_PROPBASER); - tmp = readq_relaxed(rbase + GICR_PROPBASER); + gicr_write_propbaser(val, rbase + GICR_PROPBASER); + tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { @@ -1138,7 +1138,7 @@ static void its_cpu_init_lpis(void) val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | GICR_PROPBASER_CACHEABILITY_MASK); val |= GICR_PROPBASER_nC; - writeq_relaxed(val, rbase + GICR_PROPBASER); + gicr_write_propbaser(val, rbase + GICR_PROPBASER); } pr_info_once("GIC: using cache flushing for LPI property table\n"); gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; @@ -1149,8 +1149,8 @@ static void its_cpu_init_lpis(void) GICR_PENDBASER_InnerShareable | GICR_PENDBASER_WaWb); - writeq_relaxed(val, rbase + GICR_PENDBASER); - tmp = readq_relaxed(rbase + GICR_PENDBASER); + gicr_write_pendbaser(val, rbase + GICR_PENDBASER); + tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { /* @@ -1160,7 +1160,7 @@ static void its_cpu_init_lpis(void) val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | GICR_PENDBASER_CACHEABILITY_MASK); val |= GICR_PENDBASER_nC; - writeq_relaxed(val, rbase + GICR_PENDBASER); + gicr_write_pendbaser(val, rbase + GICR_PENDBASER); } /* Enable LPIs */ @@ -1716,8 +1716,8 @@ static int __init its_probe_one(struct resource *res, (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | GITS_CBASER_VALID); - writeq_relaxed(baser, its->base + GITS_CBASER); - tmp = readq_relaxed(its->base + GITS_CBASER); + gits_write_cbaser(baser, its->base + GITS_CBASER); + tmp = gits_read_cbaser(its->base + GITS_CBASER); if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { @@ -1729,13 +1729,13 @@ static int __init its_probe_one(struct resource *res, baser &= ~(GITS_CBASER_SHAREABILITY_MASK | GITS_CBASER_CACHEABILITY_MASK); baser |= GITS_CBASER_nC; - writeq_relaxed(baser, its->base + GITS_CBASER); + gits_write_cbaser(baser, its->base + GITS_CBASER); } pr_info("ITS: using cache flushing for cmd queue\n"); its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; } - writeq_relaxed(0, its->base + GITS_CWRITER); + gits_write_cwriter(0, its->base + GITS_CWRITER); writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR); err = its_init_domain(handle, its); |