diff options
author | Cédric Le Goater <clg@kaod.org> | 2019-04-17 16:39:38 +0300 |
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committer | Joel Stanley <joel@jms.id.au> | 2021-11-01 09:42:40 +0300 |
commit | 176825ed3b123fd2189abf7c4fb7616a9f1c641a (patch) | |
tree | ecba230340d9687f394e44316dd96c3cf3ba6274 | |
parent | 1c74dec1dee99c2a15e48d0826d4a506ee64292f (diff) | |
download | linux-176825ed3b123fd2189abf7c4fb7616a9f1c641a.tar.xz |
mtd: spi-nor: aspeed: introduce a aspeed_smc_default_read() helper
OpenBMC-Staging-Count: 10
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
-rw-r--r-- | drivers/mtd/spi-nor/controllers/aspeed-smc.c | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/drivers/mtd/spi-nor/controllers/aspeed-smc.c b/drivers/mtd/spi-nor/controllers/aspeed-smc.c index 2762a018819a..e57db67e5326 100644 --- a/drivers/mtd/spi-nor/controllers/aspeed-smc.c +++ b/drivers/mtd/spi-nor/controllers/aspeed-smc.c @@ -879,6 +879,17 @@ static const uint32_t aspeed_smc_hclk_divs[] = { }; #define ASPEED_SMC_HCLK_DIV(i) (aspeed_smc_hclk_divs[(i) - 1] << 8) +static u32 aspeed_smc_default_read(struct aspeed_smc_chip *chip) +{ + return (chip->ctl_val[smc_read] & 0x2000) | + (0x00 << 28) | /* Single bit */ + (0x00 << 24) | /* CE# max */ + (0x03 << 16) | /* use normal reads */ + (0x00 << 8) | /* HCLK/16 */ + (0x00 << 6) | /* no dummy cycle */ + (0x00); /* normal mode */ +} + static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, u32 max_freq) { @@ -895,13 +906,7 @@ static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, /* We start with the dumbest setting (keep 4Byte bit) and read * some data */ - chip->ctl_val[smc_read] = (chip->ctl_val[smc_read] & 0x2000) | - (0x00 << 28) | /* Single bit */ - (0x00 << 24) | /* CE# max */ - (0x03 << 16) | /* use normal reads */ - (0x00 << 8) | /* HCLK/16 */ - (0x00 << 6) | /* no dummy cycle */ - (0x00); /* normal read */ + chip->ctl_val[smc_read] = aspeed_smc_default_read(chip); writel(chip->ctl_val[smc_read], chip->ctl); |