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authorPaul Burton <paul.burton@imgtec.com>2016-09-20 00:21:21 +0300
committerRalf Baechle <ralf@linux-mips.org>2016-10-06 18:31:00 +0300
commit422dd256642b75808cbf447040481cac11ccbefc (patch)
treedec58324328b82f805ec652203a5888ca9edfd28
parent5d2949ec86a54b73a6fc2557ef784e76c0d2cba9 (diff)
downloadlinux-422dd256642b75808cbf447040481cac11ccbefc.tar.xz
MIPS: Malta: Allow PCI devices DMA to lower 2GB physical
Set the PCI_BAR0 register in all configurations such that PCI devices can perform DMA to all of the bottom 2GB of the physical address space. This is imperfect if we make use of the legacy Malta memory map, but it is an improvement on the inconsistent values setup before. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Alexander Sverdlin <alexander.sverdlin@nokia.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14272/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/mti-malta/malta-init.c17
1 files changed, 7 insertions, 10 deletions
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index dc2c5214809d..0f3b881a3190 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -14,6 +14,7 @@
#include <linux/init.h>
#include <linux/string.h>
#include <linux/kernel.h>
+#include <linux/pci_regs.h>
#include <linux/serial_core.h>
#include <asm/cacheflush.h>
@@ -242,23 +243,19 @@ mips_pci_controller:
MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
#endif
-#ifndef CONFIG_EVA
- /* Fix up target memory mapping. */
- MSC_READ(MSC01_PCI_BAR0, mask);
- MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
-#else
+
/*
* Setup the Malta max (2GB) memory for PCI DMA in host bridge
- * in transparent addressing mode, starting from 0x80000000.
+ * in transparent addressing mode.
*/
- mask = PHYS_OFFSET | (1<<3);
+ mask = PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH;
MSC_WRITE(MSC01_PCI_BAR0, mask);
-
- mask = PHYS_OFFSET;
MSC_WRITE(MSC01_PCI_HEAD4, mask);
+
+ mask &= MSC01_PCI_BAR0_SIZE_MSK;
MSC_WRITE(MSC01_PCI_P2SCMSKL, mask);
MSC_WRITE(MSC01_PCI_P2SCMAPL, mask);
-#endif
+
/* Don't handle target retries indefinitely. */
if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
MSC01_PCI_CFG_MAXRTRY_MSK)