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author | George Hung <george.hung@quantatw.com> | 2019-05-23 15:27:34 +0300 |
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committer | Joel Stanley <joel@jms.id.au> | 2021-11-01 09:42:43 +0300 |
commit | c58e7600fd616dc55f6e4d64a715eae2903f1f8f (patch) | |
tree | d635d8d11b3e1cfbf833075d4195c94c73b1a3c5 | |
parent | 24e69e949eee0ff15ea1cb517f0b04cec5925466 (diff) | |
download | linux-c58e7600fd616dc55f6e4d64a715eae2903f1f8f.tar.xz |
dt-binding: edac: add NPCM ECC documentation
Add device tree documentation for Nuvoton BMC ECC
OpenBMC-Staging-Count: 9
Signed-off-by: George Hung <george.hung@quantatw.com>
Reviewed-by: Avi Fishman <avifishman70@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
-rw-r--r-- | Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt b/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt new file mode 100644 index 000000000000..dd4dac59a5bd --- /dev/null +++ b/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt @@ -0,0 +1,17 @@ +Nuvoton NPCM7xx SoC EDAC device driver + +The Nuvoton NPCM7xx SoC supports DDR4 memory with/without ECC and the driver +uses the EDAC framework to implement the ECC detection and corrtection. + +Required properties: +- compatible: should be "nuvoton,npcm7xx-sdram-edac" +- reg: Memory controller register set should be <0xf0824000 0x1000> +- interrupts: should be MC interrupt #25 + +Example: + + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm7xx-sdram-edac"; + reg = <0xf0824000 0x1000>; + interrupts = <0 25 4>; + }; |