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| author | Matt Roper <matthew.d.roper@intel.com> | 2021-07-29 19:59:59 +0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-08-04 07:09:42 +0300 |
| commit | eb962fae0078d6f827473e0eb6019db55d2217f1 (patch) | |
| tree | 73a477d9aca21124df3015826dd547b68ad0a0d5 | |
| parent | 05b78d291d3854aeae5cfd19cc860910b1a8fcdc (diff) | |
| download | linux-eb962fae0078d6f827473e0eb6019db55d2217f1.tar.xz | |
drm/i915/xehpsdv: Add maximum sseu limits
Due to the removal of legacy slices and the transition to a
gslice/cslice/mslice/etc. design, we'll internally store all DSS under
"slice0."
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Caz Yokoyama <caz.yokoyama@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210729170008.2836648-10-matthew.d.roper@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_sseu.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_sseu.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 2 |
3 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index d2d5c47ef5c3..3a2ff0e00b65 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -145,7 +145,10 @@ static void gen12_sseu_info_init(struct intel_gt *gt) * across the entire device. Then calculate out the DSS for each * workload type within that software slice. */ - intel_sseu_set_info(sseu, 1, 6, 16); + if (IS_XEHPSDV(gt->i915)) + intel_sseu_set_info(sseu, 1, 32, 16); + else + intel_sseu_set_info(sseu, 1, 6, 16); /* * As mentioned above, Xe_HP does not have the concept of a slice. diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index 8d85ec05f610..05a93e4e66cb 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -16,7 +16,7 @@ struct intel_gt; struct drm_printer; #define GEN_MAX_SLICES (3) /* SKL upper bound */ -#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ +#define GEN_MAX_SUBSLICES (32) /* XEHPSDV upper bound */ #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE) #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES) #define GEN_MAX_EUS (16) /* TGL upper bound */ diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c index 5e7b09c5e36f..1ba8b7da9d37 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c @@ -53,7 +53,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt, static void gen11_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) { -#define SS_MAX 6 +#define SS_MAX 8 struct intel_uncore *uncore = gt->uncore; const struct intel_gt_info *info = >->info; u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; |