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authorDavid S. Miller <davem@davemloft.net>2016-06-11 09:24:55 +0300
committerDavid S. Miller <davem@davemloft.net>2016-06-11 09:24:55 +0300
commit7a04c012839eefaef9451300ed272b5a9c48821f (patch)
tree2239c99f470a89b420ca902b40c8d5731469676b /Documentation/devicetree/bindings/phy/brcm,mdio-mux-bus-pci.txt
parentd46e416c11c88ef1deb5c7f19271806a5be597fe (diff)
parent4484f730b3358363ca4b3b422354676581fab2cb (diff)
downloadlinux-7a04c012839eefaef9451300ed272b5a9c48821f.tar.xz
Merge branch 'mdio-iProc-SOC'
Pramod Kumar says: ==================== Add MDIO bus multiplexer support for iProc SoCs Broadcom iProc based SoCs use a MDIO bus multiplexer where child buses could be internal as well external to SoCs. These buses could supports MDIO transaction compatible to C-22/C-45. Broadcom MDIO bus multiplexer is an integrated multiplexer where child bus selection and mdio transaction logic lies inside multiplexer itself. To accommodate this multiplexer in existing mux framework below changes were required- 1. Passed MDIO parent bus via mdio_mux_init to MDIO mux framework. This patch set includes MDIO bus multiplexer driver along with above framework change. It includes one external bus node having Ethernet PHY attached and two internal bus node holding PCIe PHYs. This patch series is based on v4.7-rc1 and is available from github- repo: https://github.com/Broadcom/arm64-linux.git branch:mdio-mux-v5 -Changes from v4: - disabled PCIe PHYs from dtsi and enabled in dts file. -Changes from v3: - Unregister and free the parent MDIO bus. - rebased on net-next/master branch. Reason for resend: -Rebased on v4.7-rc1 Changes from v2: -Addressed Rob's comments in this patch regarding typo/grammers. -Addressed David's comments regarding local variables order. -Removed property "mdio-integrated-mux" and used mdiobus_register() in place of of_mdiobus_regsiter(). -removed usage of IS_ERR_OR_NULL to IS_ERR in PCIe PHY driver. Changes from v1: - stop using "brcm,is_c45" from bus node as suggested by Andrew. MDIO PHY driver will logically OR MII_ADDR_C45 into the address when issues any C45 MDIO read/write transaction. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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+* Broadcom NS2 PCIe PHY binding document
+
+Required bus properties:
+- reg: MDIO Bus number for the MDIO interface
+- #address-cells: must be 1
+- #size-cells: must be 0
+
+Required PHY properties:
+- compatible: should be "brcm,ns2-pcie-phy"
+- reg: MDIO Phy ID for the MDIO interface
+- #phy-cells: must be 0
+
+This is a child bus node of "brcm,mdio-mux-iproc" node.
+
+Example:
+
+mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pci_phy0: pci-phy@0 {
+ compatible = "brcm,ns2-pcie-phy";
+ reg = <0x0>;
+ #phy-cells = <0>;
+ };
+};