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authorStephen Boyd <sboyd@kernel.org>2019-07-12 21:10:52 +0300
committerStephen Boyd <sboyd@kernel.org>2019-07-12 21:10:52 +0300
commit1f5d580cabc6bdc595116f4ca16cfb226f2b8b5c (patch)
tree53919af912ec25ba0e7da091f1c1fbc86a561040 /Documentation/devicetree
parentb6bb2bc2fd15fefabc7c82d3542e6537a5d9e7db (diff)
parentf02fba3aa8feeee0a9f9c82c6db2ae9dda7825cd (diff)
parent4abf9adc12c6ed4df158029a7381a0004d10117a (diff)
parente5bbbff5b7d7e76ccfe922a014ba628c558eff2f (diff)
parentce9a1046434caee1d4c33a63712fdb18e6904a02 (diff)
parentafa88bdbf19314494415d622d50730b5d854dd91 (diff)
downloadlinux-1f5d580cabc6bdc595116f4ca16cfb226f2b8b5c.tar.xz
Merge branches 'clk-qcom-gdsc-warn', 'clk-ingenic', 'clk-qcom-qcs404-reset', 'clk-xgene-limit' and 'clk-meson' into clk-next
* clk-qcom-gdsc-warn: clk: qcom: gdsc: WARN when failing to toggle * clk-ingenic: MIPS: Remove dead code clk: ingenic: Remove unused functions MIPS: jz4740: PM: Let CGU driver suspend clocks and set sleep mode clk: ingenic: Handle setting the Low-Power Mode bit clk: ingenic: Add missing header in cgu.h clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly clk: ingenic/jz4725b: Fix incorrect dividers for main clocks clk: ingenic/jz4770: Fix incorrect dividers for main clocks clk: ingenic/jz4740: Fix incorrect dividers for main clocks clk: ingenic: Add support for divider tables * clk-qcom-qcs404-reset: clk: gcc-qcs404: Add PCIe resets * clk-xgene-limit: clk: xgene: Don't build COMMON_CLK_XGENE by default * clk-meson: clk: meson: g12a: mark fclk_div3 as critical clk: meson: g12a: Add support for G12B CPUB clocks dt-bindings: clk: meson: add g12b periph clock controller bindings clk: meson-g12a: add temperature sensor clocks dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs clk: meson: meson8b: add the cts_i958 clock clk: meson: meson8b: add the cts_mclk_i958 clocks clk: meson: meson8b: add the cts_amclk clocks dt-bindings: clock: meson8b: add the audio clocks clk: meson: g12a: add controller register init clk: meson: eeclk: add init regs clk: meson: g12a: add mpll register init sequences clk: meson: mpll: add init callback and regs clk: meson: axg: spread spectrum is on mpll2 clk: meson: gxbb: no spread spectrum on mpll0 clk: meson: mpll: properly handle spread spectrum clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo