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| author | David S. Miller <davem@davemloft.net> | 2014-05-24 08:32:30 +0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-05-24 08:32:30 +0400 |
| commit | 54e5c4def0614ab540fbdf68e45342a4af141702 (patch) | |
| tree | 95a2f61c72336932e83d9e4180cd9739106d624b /arch/arm/mach-omap2/omap-headsmp.S | |
| parent | be65de7174123e02477bd488db1a657caf0f9947 (diff) | |
| parent | 1ee1ceafb572f1a925809168267a7962a4289de8 (diff) | |
| download | linux-54e5c4def0614ab540fbdf68e45342a4af141702.tar.xz | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts:
drivers/net/bonding/bond_alb.c
drivers/net/ethernet/altera/altera_msgdma.c
drivers/net/ethernet/altera/altera_sgdma.c
net/ipv6/xfrm6_output.c
Several cases of overlapping changes.
The xfrm6_output.c has a bug fix which overlaps the renaming
of skb->local_df to skb->ignore_df.
In the Altera TSE driver cases, the register access cleanups
in net-next overlapped with bug fixes done in net.
Similarly a bug fix to send ALB packets in the bonding driver using
the right source address overlaps with cleanups in net-next.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/arm/mach-omap2/omap-headsmp.S')
| -rw-r--r-- | arch/arm/mach-omap2/omap-headsmp.S | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 75e92952c18e..40c5d5f1451c 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -1,7 +1,7 @@ /* * Secondary CPU startup routine source file. * - * Copyright (C) 2009 Texas Instruments, Inc. + * Copyright (C) 2009-2014 Texas Instruments, Inc. * * Author: * Santosh Shilimkar <santosh.shilimkar@ti.com> @@ -28,9 +28,13 @@ * code. This routine also provides a holding flag into which * secondary core is held until we're ready for it to initialise. * The primary core will update this flag using a hardware -+ * register AuxCoreBoot0. + * register AuxCoreBoot0. */ ENTRY(omap5_secondary_startup) +.arm +THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode. +THUMB( bx r9 ) @ If this is a Thumb-2 kernel, +THUMB( .thumb ) @ switch to Thumb now. wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 ldr r0, [r2] mov r0, r0, lsr #5 |