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author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-01-07 03:50:35 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-01-07 03:50:35 +0300 |
commit | 3c0cb7c31c206aaedb967e44b98442bbeb17a6c4 (patch) | |
tree | 3ecba45d7ffae4fba4a5aafaef4af5b0b1105bde /arch/arm/mach-pxa/balloon3.c | |
parent | f70f5b9dc74ca7d0a64c4ead3fb28da09dc1b234 (diff) | |
parent | 404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34 (diff) | |
download | linux-3c0cb7c31c206aaedb967e44b98442bbeb17a6c4.tar.xz |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (416 commits)
ARM: DMA: add support for DMA debugging
ARM: PL011: add DMA burst threshold support for ST variants
ARM: PL011: Add support for transmit DMA
ARM: PL011: Ensure IRQs are disabled in UART interrupt handler
ARM: PL011: Separate hardware FIFO size from TTY FIFO size
ARM: PL011: Allow better handling of vendor data
ARM: PL011: Ensure error flags are clear at startup
ARM: PL011: include revision number in boot-time port printk
ARM: vexpress: add sched_clock() for Versatile Express
ARM i.MX53: Make MX53 EVK bootable
ARM i.MX53: Some bug fix about MX53 MSL code
ARM: 6607/1: sa1100: Update platform device registration
ARM: 6606/1: sa1100: Fix platform device registration
ARM i.MX51: rename IPU irqs
ARM i.MX51: Add ipu clock support
ARM: imx/mx27_3ds: Add PMIC support
ARM: DMA: Replace page_to_dma()/dma_to_page() with pfn_to_dma()/dma_to_pfn()
mx51: fix usb clock support
MX51: Add support for usb host 2
arch/arm/plat-mxc/ehci.c: fix errors/typos
...
Diffstat (limited to 'arch/arm/mach-pxa/balloon3.c')
-rw-r--r-- | arch/arm/mach-pxa/balloon3.c | 59 |
1 files changed, 35 insertions, 24 deletions
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index 21e188901935..ccb2d0cebcc3 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -567,27 +567,29 @@ static inline void balloon3_i2c_init(void) {} * NAND ******************************************************************************/ #if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE) -static uint16_t balloon3_ctl = - BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | - BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 | - BALLOON3_NAND_CONTROL_FLWP; - static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; + uint8_t balloon3_ctl_set = 0, balloon3_ctl_clr = 0; if (ctrl & NAND_CTRL_CHANGE) { if (ctrl & NAND_CLE) - balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCLE; + balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLCLE; else - balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLCLE; + balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLCLE; if (ctrl & NAND_ALE) - balloon3_ctl |= BALLOON3_NAND_CONTROL_FLALE; + balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLALE; else - balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLALE; - - __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); + balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLALE; + + if (balloon3_ctl_clr) + __raw_writel(balloon3_ctl_clr, + BALLOON3_NAND_CONTROL_REG); + if (balloon3_ctl_set) + __raw_writel(balloon3_ctl_set, + BALLOON3_NAND_CONTROL_REG | + BALLOON3_FPGA_SETnCLR); } if (cmd != NAND_CMD_NONE) @@ -599,28 +601,33 @@ static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip) if (chip < 0 || chip > 3) return; - balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCE0 | - BALLOON3_NAND_CONTROL_FLCE1 | - BALLOON3_NAND_CONTROL_FLCE2 | - BALLOON3_NAND_CONTROL_FLCE3; + /* Assert all nCE lines */ + __raw_writew( + BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | + BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3, + BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR); /* Deassert correct nCE line */ - balloon3_ctl &= ~(BALLOON3_NAND_CONTROL_FLCE0 << chip); + __raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip, + BALLOON3_NAND_CONTROL_REG); +} - __raw_writew(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); +static int balloon3_nand_dev_ready(struct mtd_info *mtd) +{ + return __raw_readl(BALLOON3_NAND_STAT_REG) & BALLOON3_NAND_STAT_RNB; } static int balloon3_nand_probe(struct platform_device *pdev) { - void __iomem *temp_map; uint16_t ver; int ret; - __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, BALLOON3_NAND_CONTROL2_REG); + __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, + BALLOON3_NAND_CONTROL2_REG | BALLOON3_FPGA_SETnCLR); ver = __raw_readw(BALLOON3_FPGA_VER); - if (ver > 0x0201) - pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. " + if (ver < 0x4f08) + pr_warn("The FPGA code, version 0x%04x, is too old. " "NAND support might be broken in this version!", ver); /* Power up the NAND chips */ @@ -635,7 +642,11 @@ static int balloon3_nand_probe(struct platform_device *pdev) gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1); /* Deassert all nCE lines and write protect line */ - __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); + __raw_writel( + BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | + BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 | + BALLOON3_NAND_CONTROL_FLWP, + BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR); return 0; err2: @@ -677,7 +688,7 @@ struct platform_nand_data balloon3_nand_pdata = { }, .ctrl = { .hwcontrol = 0, - .dev_ready = 0, + .dev_ready = balloon3_nand_dev_ready, .select_chip = balloon3_nand_select_chip, .cmd_ctrl = balloon3_nand_cmd_ctl, .probe = balloon3_nand_probe, @@ -802,7 +813,7 @@ static struct map_desc balloon3_io_desc[] __initdata = { static void __init balloon3_map_io(void) { - pxa_map_io(); + pxa27x_map_io(); iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc)); } |