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author | Steven Price <steven.price@arm.com> | 2019-12-16 14:56:31 +0300 |
---|---|---|
committer | Will Deacon <will@kernel.org> | 2020-01-16 13:44:14 +0300 |
commit | 275fa0ea2cf7a84450f9c0ec0d9e7ec168ed2e2d (patch) | |
tree | 1a14bb38c7438a57a0f21266e1f81f5d0aed7186 /arch/arm64/include/asm/kvm_hyp.h | |
parent | db0d46a58d34c7cd9d5ece98daf4b8afe3d770f8 (diff) | |
download | linux-275fa0ea2cf7a84450f9c0ec0d9e7ec168ed2e2d.tar.xz |
arm64: Workaround for Cortex-A55 erratum 1530923
Cortex-A55 erratum 1530923 allows TLB entries to be allocated as a
result of a speculative AT instruction. This may happen in the middle of
a guest world switch while the relevant VMSA configuration is in an
inconsistent state, leading to erroneous content being allocated into
TLBs.
The same workaround as is used for Cortex-A76 erratum 1165522
(WORKAROUND_SPECULATIVE_AT_VHE) can be used here. Note that this
mandates the use of VHE on affected parts.
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Steven Price <steven.price@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include/asm/kvm_hyp.h')
-rw-r--r-- | arch/arm64/include/asm/kvm_hyp.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h index 167a161dd596..a3a6a2ba9a63 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -91,8 +91,8 @@ static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm) write_sysreg(kvm_get_vttbr(kvm), vttbr_el2); /* - * ARM erratum 1165522 requires the actual execution of the above - * before we can switch to the EL1/EL0 translation regime used by + * ARM errata 1165522 and 1530923 require the actual execution of the + * above before we can switch to the EL1/EL0 translation regime used by * the guest. */ asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE)); |