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| author | Anshuman Khandual <anshuman.khandual@arm.com> | 2020-07-03 06:51:34 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2020-07-03 18:52:04 +0300 |
| commit | bc67f10ad1d76a30e01c539c0043417fa34648d7 (patch) | |
| tree | da5a0161ca2b94e908fccc9f4b757f2b69bef69a /arch/arm64/include/asm/sysreg.h | |
| parent | 9ebcfadb0610322ac537dd7aa5d9cbc2b2894c68 (diff) | |
| download | linux-bc67f10ad1d76a30e01c539c0043417fa34648d7.tar.xz | |
arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register
Enable EVC, FGT, EXS features bits in ID_AA64MMFR0 register as per ARM DDI
0487F.a specification.
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Link: https://lore.kernel.org/r/1593748297-1965-2-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 463175f80341..2e36dfde2570 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -706,6 +706,9 @@ #define ID_AA64ZFR0_SVEVER_SVE2 0x1 /* id_aa64mmfr0 */ +#define ID_AA64MMFR0_ECV_SHIFT 60 +#define ID_AA64MMFR0_FGT_SHIFT 56 +#define ID_AA64MMFR0_EXS_SHIFT 44 #define ID_AA64MMFR0_TGRAN4_2_SHIFT 40 #define ID_AA64MMFR0_TGRAN64_2_SHIFT 36 #define ID_AA64MMFR0_TGRAN16_2_SHIFT 32 |