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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-02 02:07:19 +0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-02 02:07:19 +0400
commitb4beb4bf9934d151bf4581a54ae028927374cb2a (patch)
tree28475f62b18784e1d10b05e901799d02c054587f /arch/arm
parentf3c3f0670501fee130f22193369249deea8cc630 (diff)
parent3945fe9314af718946f71185901c28dd349469c7 (diff)
downloadlinux-b4beb4bf9934d151bf4581a54ae028927374cb2a.tar.xz
Merge branch 'for-linus/i2c-3.2' of git://git.fluff.org/bjdooks/linux
* 'for-linus/i2c-3.2' of git://git.fluff.org/bjdooks/linux: (47 commits) i2c-s3c2410: Add device tree support i2c-s3c2410: Keep a copy of platform data and use it i2c-nomadik: cosmetic coding style corrections i2c-au1550: dev_pm_ops conversion i2c-au1550: increase timeout waiting for master done i2c-au1550: remove unused ack_timeout i2c-au1550: remove usage of volatile keyword i2c-tegra: __iomem annotation fix i2c-eg20t: Add initialize processing in case i2c-error occurs i2c-eg20t: Fix flag setting issue i2c-eg20t: add stop sequence in case wait-event timeout occurs i2c-eg20t: Separate error processing i2c-eg20t: Fix 10bit access issue i2c-eg20t: Modify returned value s32 to long i2c-eg20t: Fix bus-idle waiting issue i2c-designware: Fix PCI core warning on suspend/resume i2c-designware: Add runtime power management support i2c-designware: Add support for Designware core behind PCI devices. i2c-designware: Push all register reads/writes into the core code. i2c-designware: Support multiple cores using same ISR ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-mxc/include/mach/i2c.h4
-rw-r--r--arch/arm/plat-omap/i2c.c27
2 files changed, 27 insertions, 4 deletions
diff --git a/arch/arm/plat-mxc/include/mach/i2c.h b/arch/arm/plat-mxc/include/mach/i2c.h
index 4a5dc5c6d8e8..375cdd0cf876 100644
--- a/arch/arm/plat-mxc/include/mach/i2c.h
+++ b/arch/arm/plat-mxc/include/mach/i2c.h
@@ -11,14 +11,10 @@
/**
* struct imxi2c_platform_data - structure of platform data for MXC I2C driver
- * @init: Initialise gpio's and other board specific things
- * @exit: Free everything initialised by @init
* @bitrate: Bus speed measured in Hz
*
**/
struct imxi2c_platform_data {
- int (*init)(struct device *dev);
- void (*exit)(struct device *dev);
int bitrate;
};
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 3341ca4703e9..2388b8eebaaa 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -108,6 +108,22 @@ static inline int omap1_i2c_add_bus(int bus_id)
res[1].start = INT_I2C;
pdata = &i2c_pdata[bus_id - 1];
+ /* all OMAP1 have IP version 1 register set */
+ pdata->rev = OMAP_I2C_IP_VERSION_1;
+
+ /* all OMAP1 I2C are implemented like this */
+ pdata->flags = OMAP_I2C_FLAG_NO_FIFO |
+ OMAP_I2C_FLAG_SIMPLE_CLOCK |
+ OMAP_I2C_FLAG_16BIT_DATA_REG |
+ OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK;
+
+ /* how the cpu bus is wired up differs for 7xx only */
+
+ if (cpu_is_omap7xx())
+ pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1;
+ else
+ pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2;
+
return platform_device_register(pdev);
}
@@ -138,6 +154,7 @@ static inline int omap2_i2c_add_bus(int bus_id)
struct omap_device *od;
char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
struct omap_i2c_bus_platform_data *pdata;
+ struct omap_i2c_dev_attr *dev_attr;
omap2_i2c_mux_pins(bus_id);
@@ -152,6 +169,16 @@ static inline int omap2_i2c_add_bus(int bus_id)
pdata = &i2c_pdata[bus_id - 1];
/*
+ * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
+ * use, and functionality implementation flags, up to the OMAP I2C
+ * driver via platform data
+ */
+ pdata->rev = oh->class->rev;
+
+ dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
+ pdata->flags = dev_attr->flags;
+
+ /*
* When waiting for completion of a i2c transfer, we need to
* set a wake up latency constraint for the MPU. This is to
* ensure quick enough wakeup from idle, when transfer