diff options
| author | Guo Ren <guoren@linux.alibaba.com> | 2020-09-07 09:20:18 +0300 |
|---|---|---|
| committer | Guo Ren <guoren@linux.alibaba.com> | 2021-01-12 04:52:40 +0300 |
| commit | 0c8a32eed1625a65798286fb73fea8710a908545 (patch) | |
| tree | 69992b6e217f5e985ebbf1f739b2af336d89138c /arch/csky/kernel/head.S | |
| parent | 7c53f6b671f4aba70ff15e1b05148b10d58c2837 (diff) | |
| download | linux-0c8a32eed1625a65798286fb73fea8710a908545.tar.xz | |
csky: Add memory layout 2.5G(user):1.5G(kernel)
There are two ways for translating va to pa for csky:
- Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk)
- Use SSEG0/1 (Simple Segment Mapping)
We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1
are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0
to use 2G-2.5G as TLB user mapping.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'arch/csky/kernel/head.S')
| -rw-r--r-- | arch/csky/kernel/head.S | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/csky/kernel/head.S b/arch/csky/kernel/head.S index 17ed9d250480..7e3e4f15b052 100644 --- a/arch/csky/kernel/head.S +++ b/arch/csky/kernel/head.S @@ -21,10 +21,16 @@ END(_start) ENTRY(_start_smp_secondary) SETUP_MMU - /* copy msa1 from CPU0 */ - lrw r6, secondary_msa1 +#ifdef CONFIG_PAGE_OFFSET_80000000 + lrw r6, secondary_msa1 ld.w r6, (r6, 0) mtcr r6, cr<31, 15> +#endif + + lrw r6, secondary_pgd + ld.w r6, (r6, 0) + mtcr r6, cr<28, 15> + mtcr r6, cr<29, 15> /* set stack point */ lrw r6, secondary_stack |