diff options
| author | James Hogan <james.hogan@imgtec.com> | 2016-05-11 15:50:51 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 16:30:25 +0300 |
| commit | e06a1548f3043febb658b58ec5ccbc7d03a785af (patch) | |
| tree | 4bf416b2262006e60bd3b81c24d089c03f5f3e37 /arch/mips/include/asm/cpu.h | |
| parent | 37fb60f8e3f011c25c120081a73886ad8dbc42fd (diff) | |
| download | linux-e06a1548f3043febb658b58ec5ccbc7d03a785af.tar.xz | |
MIPS: Add defs & probing of BadInstr[P] registers
The optional CP0_BadInstr and CP0_BadInstrP registers are written with
the encoding of the instruction that caused a synchronous exception to
occur, and the prior branch instruction if in a delay slot.
These will be useful for instruction emulation in KVM, and especially
for VZ support where reading guest virtual memory is a bit more awkward.
Add CPU option numbers and cpu_has_* definitions to indicate the
presence of each registers, and add code to probe for them using bits in
the CP0_Config3 register.
[ralf@linux-mips.org: resolve merge conflict.]
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13224/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu.h')
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 3108d9b35bf1..0cf90d67c1af 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -405,6 +405,8 @@ enum cpu_type_enum { #define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */ #define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */ #define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */ +#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */ +#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */ /* * CPU ASE encodings |