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| author | Kevin Cernekee <cernekee@gmail.com> | 2014-10-21 08:27:58 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-11-24 09:45:11 +0300 |
| commit | bbf2ba67cdbdb3676a661c3eba5572d1e513627f (patch) | |
| tree | 92cdfa8bfd348cacb28b4cd70117afe5d762ec8d /arch/mips/kernel/smp-bmips.c | |
| parent | a7ef1eaddbf4bd50bfee92d9dfbecadc61467bbf (diff) | |
| download | linux-bbf2ba67cdbdb3676a661c3eba5572d1e513627f.tar.xz | |
MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUs
BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2
line size. If L1_CACHE_SHIFT is undersized, DMA buffers will not be
cacheline-aligned and terrible things will happen.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8164/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/smp-bmips.c')
0 files changed, 0 insertions, 0 deletions