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authorPaul Burton <paul.burton@mips.com>2019-05-01 01:53:31 +0300
committerPaul Burton <paul.burton@mips.com>2019-05-02 21:20:59 +0300
commit783454e2bc7ce491b5cd50154433cde993bfd849 (patch)
tree3b8906fb5290e2a80dfefa92f5b5ccb3e70d2299 /arch/mips/kernel
parent172dcd935c34b022729f45a7bbaae5cc05231533 (diff)
downloadlinux-783454e2bc7ce491b5cd50154433cde993bfd849.tar.xz
MIPS: Sync icache for whole exception vector
Rather than performing cache flushing for a fixed 0x400 bytes, use the actual size of the vector in order to ensure we cover all emitted code on systems that make use of vectored interrupts. Signed-off-by: Paul Burton <paul.burton@mips.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Tested-by: Serge Semin <fancer.lancer@gmail.com> Cc: linux-mips@vger.kernel.org
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/traps.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 9b565ed51662..2775190adbe7 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2454,7 +2454,7 @@ void __init trap_init(void)
else
set_handler(0x080, &except_vec3_generic, 0x80);
- local_flush_icache_range(ebase, ebase + 0x400);
+ local_flush_icache_range(ebase, ebase + vec_size);
sort_extable(__start___dbe_table, __stop___dbe_table);