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authorRalf Baechle <ralf@linux-mips.org>2016-01-27 20:16:15 +0300
committerRalf Baechle <ralf@linux-mips.org>2016-05-13 15:01:38 +0300
commit7c8196fd43e41e7b699d2f7a54bafd10dd2f65bb (patch)
treec05b6a3ed94a1be46c11e64407467f5f3d90646d /arch/mips/pmcs-msp71xx
parent9329c154e4a8a253347829c1d8cc416061cc055a (diff)
downloadlinux-7c8196fd43e41e7b699d2f7a54bafd10dd2f65bb.tar.xz
MIPS: MSP71xx: Use __flush_cache_all instead of flush_cache_all.
Flushing caches is probably sensible on reset but flush_cache_all has been a no-op for a very long time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pmcs-msp71xx')
-rw-r--r--arch/mips/pmcs-msp71xx/msp_setup.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/pmcs-msp71xx/msp_setup.c b/arch/mips/pmcs-msp71xx/msp_setup.c
index 9d293b3e9130..a63b73610fd4 100644
--- a/arch/mips/pmcs-msp71xx/msp_setup.c
+++ b/arch/mips/pmcs-msp71xx/msp_setup.c
@@ -118,7 +118,7 @@ void msp_restart(char *command)
/* No chip-specific reset code, just jump to the ROM reset vector */
set_c0_status(ST0_BEV | ST0_ERL);
change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
- flush_cache_all();
+ __flush_cache_all();
write_c0_wired(0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));