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authorPetr Cvek <petrcvekcz@gmail.com>2019-06-21 00:39:38 +0300
committerPaul Burton <paul.burton@mips.com>2019-06-25 00:15:04 +0300
commitf0dd300101f316fefb19710ae83bcc97a72cdf68 (patch)
tree68cc3ec7321dbdad1d4ad4095b1efddbc543307d /arch/mips
parentba1bc0fcdeaf3bf583c1517bd2e3e29cf223c969 (diff)
downloadlinux-f0dd300101f316fefb19710ae83bcc97a72cdf68.tar.xz
MIPS: lantiq: Shorten register names, remove unused macros
The macros LTQ_ICU_IM1_ISR and LTQ_ICU_OFFSET seems to be unused, remove them. Allong with that, remove _IM0 substring from the macro names. The IM (interrupt module) is already defined in IOMEM access and IM0 would be misleading. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: hauke@hauke-m.de Cc: john@phrozen.org Cc: linux-mips@vger.kernel.org Cc: openwrt-devel@lists.openwrt.org Cc: pakahmar@hotmail.com
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/lantiq/irq.c34
1 files changed, 16 insertions, 18 deletions
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 35d7c5f6d159..b9ca20ff07d5 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -22,13 +22,11 @@
#include <irq.h>
/* register definitions - internal irqs */
-#define LTQ_ICU_IM0_ISR 0x0000
-#define LTQ_ICU_IM0_IER 0x0008
-#define LTQ_ICU_IM0_IOSR 0x0010
-#define LTQ_ICU_IM0_IRSR 0x0018
-#define LTQ_ICU_IM0_IMR 0x0020
-#define LTQ_ICU_IM1_ISR 0x0028
-#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
+#define LTQ_ICU_ISR 0x0000
+#define LTQ_ICU_IER 0x0008
+#define LTQ_ICU_IOSR 0x0010
+#define LTQ_ICU_IRSR 0x0018
+#define LTQ_ICU_IMR 0x0020
/* register definitions - external irqs */
#define LTQ_EIU_EXIN_C 0x0000
@@ -77,8 +75,8 @@ void ltq_disable_irq(struct irq_data *d)
unsigned long im = offset / INT_NUM_IM_OFFSET;
offset %= INT_NUM_IM_OFFSET;
- ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset),
- LTQ_ICU_IM0_IER);
+ ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) & ~BIT(offset),
+ LTQ_ICU_IER);
}
void ltq_mask_and_ack_irq(struct irq_data *d)
@@ -87,9 +85,9 @@ void ltq_mask_and_ack_irq(struct irq_data *d)
unsigned long im = offset / INT_NUM_IM_OFFSET;
offset %= INT_NUM_IM_OFFSET;
- ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset),
- LTQ_ICU_IM0_IER);
- ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR);
+ ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) & ~BIT(offset),
+ LTQ_ICU_IER);
+ ltq_icu_w32(im, BIT(offset), LTQ_ICU_ISR);
}
static void ltq_ack_irq(struct irq_data *d)
@@ -98,7 +96,7 @@ static void ltq_ack_irq(struct irq_data *d)
unsigned long im = offset / INT_NUM_IM_OFFSET;
offset %= INT_NUM_IM_OFFSET;
- ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR);
+ ltq_icu_w32(im, BIT(offset), LTQ_ICU_ISR);
}
void ltq_enable_irq(struct irq_data *d)
@@ -107,8 +105,8 @@ void ltq_enable_irq(struct irq_data *d)
unsigned long im = offset / INT_NUM_IM_OFFSET;
offset %= INT_NUM_IM_OFFSET;
- ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) | BIT(offset),
- LTQ_ICU_IM0_IER);
+ ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IER) | BIT(offset),
+ LTQ_ICU_IER);
}
static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
@@ -225,7 +223,7 @@ static void ltq_hw_irq_handler(struct irq_desc *desc)
u32 irq;
irq_hw_number_t hwirq;
- irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
+ irq = ltq_icu_r32(module, LTQ_ICU_IOSR);
if (irq == 0)
return;
@@ -288,9 +286,9 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
/* turn off all irqs by default */
for (i = 0; i < MAX_IM; i++) {
/* make sure all irqs are turned off by default */
- ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
+ ltq_icu_w32(i, 0, LTQ_ICU_IER);
/* clear all possibly pending interrupts */
- ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
+ ltq_icu_w32(i, ~0, LTQ_ICU_ISR);
}
mips_cpu_irq_init();