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authorRadha Mohan Chintakuntla <rchintakuntla@cavium.com>2017-10-11 08:37:51 +0300
committerTejun Heo <tj@kernel.org>2017-10-11 17:08:13 +0300
commitb1314e3f85b36ce1311d7242085f6dd93709c694 (patch)
treeaee05713dac6c2b4ebca4ad6bdb9423a758dbe20 /drivers/ata/ahci.c
parent03b623fbc5d8d24d45d4e8cd4ba245b0170891f3 (diff)
downloadlinux-b1314e3f85b36ce1311d7242085f6dd93709c694.tar.xz
ahci: Add support for Cavium's fifth generation SATA controller
This patch adds support for Cavium's fifth generation SATA controller. It is an on-chip controller and complies with AHCI 1.3.1. As the controller uses 64-bit addresses it cannot use the standard AHCI BAR5 and so uses BAR4. Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'drivers/ata/ahci.c')
-rw-r--r--drivers/ata/ahci.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index cb9b0e9090e3..6e26c1c2d18c 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -57,6 +57,7 @@ enum {
AHCI_PCI_BAR_STA2X11 = 0,
AHCI_PCI_BAR_CAVIUM = 0,
AHCI_PCI_BAR_ENMOTUS = 2,
+ AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
AHCI_PCI_BAR_STANDARD = 5,
};
@@ -1567,8 +1568,12 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
- else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
- ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
+ else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
+ if (pdev->device == 0xa01c)
+ ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
+ if (pdev->device == 0xa084)
+ ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
+ }
/* acquire resources */
rc = pcim_enable_device(pdev);