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authorJames Liao <jamesjj.liao@mediatek.com>2015-07-28 10:37:34 +0300
committerJames Liao <jamesjj.liao@mediatek.com>2015-10-01 07:04:49 +0300
commite02940fc9ed323ae512f3ded62abaf9d6a3d3265 (patch)
tree29d6a642c135c6f6b1e6147855ffd8741b48c73b /drivers/clk/mediatek/clk-mt8173.c
parent07d130698b8e1ecf1a72d294b5f89a26fea1ec6f (diff)
downloadlinux-e02940fc9ed323ae512f3ded62abaf9d6a3d3265.tar.xz
clk: mediatek: Add __initdata and __init for data and functions
Add __init for clock registration functions, and add __initdata for mtk_gate_regs initial structures. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt8173.c')
-rw-r--r--drivers/clk/mediatek/clk-mt8173.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 63e32fdb660f..849507a02ec1 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -587,7 +587,7 @@ static const struct mtk_composite top_muxes[] __initconst = {
MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
};
-static const struct mtk_gate_regs infra_cg_regs = {
+static const struct mtk_gate_regs infra_cg_regs __initconst = {
.set_ofs = 0x0040,
.clr_ofs = 0x0044,
.sta_ofs = 0x0048,
@@ -620,13 +620,13 @@ static const struct mtk_fixed_factor infra_divs[] __initconst = {
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
};
-static const struct mtk_gate_regs peri0_cg_regs = {
+static const struct mtk_gate_regs peri0_cg_regs __initconst = {
.set_ofs = 0x0008,
.clr_ofs = 0x0010,
.sta_ofs = 0x0018,
};
-static const struct mtk_gate_regs peri1_cg_regs = {
+static const struct mtk_gate_regs peri1_cg_regs __initconst = {
.set_ofs = 0x000c,
.clr_ofs = 0x0014,
.sta_ofs = 0x001c,