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authorJames Liao <jamesjj.liao@mediatek.com>2015-07-10 11:39:33 +0300
committerStephen Boyd <sboyd@codeaurora.org>2015-07-28 21:58:54 +0300
commit196de71a9d9e9090406a87362d22b67ae633fa7a (patch)
tree615be1dddf4c657e5114458cfae75d5e4e6ad6d7 /drivers/clk/mediatek
parentb3be457e5854e3095cd0be850058c765aaf467ab (diff)
downloadlinux-196de71a9d9e9090406a87362d22b67ae633fa7a.tar.xz
clk: mediatek: Fix calculation of PLL rate settings
Avoid u32 overflow when calculate post divider setting, and increase the max post divider setting from 3 (/8) to 4 (/16). Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek')
-rw-r--r--drivers/clk/mediatek/clk-pll.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 68af5183cda0..0e3f4ef0e871 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -144,9 +144,9 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
if (freq > pll->data->fmax)
freq = pll->data->fmax;
- for (val = 0; val < 4; val++) {
+ for (val = 0; val < 5; val++) {
*postdiv = 1 << val;
- if (freq * *postdiv >= fmin)
+ if ((u64)freq * *postdiv >= fmin)
break;
}