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authorArnd Bergmann <arnd@arndb.de>2013-04-09 18:31:43 +0400
committerArnd Bergmann <arnd@arndb.de>2013-04-09 18:31:43 +0400
commit3be1812ea3b7193ee1a3993cadf9a7985121cf16 (patch)
tree4aed605da38588bae8544dccdf6f81004d02ee0b /drivers/clk
parent759417ac74fedf74af9c1c1510a9e4e15b951239 (diff)
parent6affb4826405dc1f53bae0e5c302a18f734a44ca (diff)
downloadlinux-3be1812ea3b7193ee1a3993cadf9a7985121cf16.tar.xz
Merge branch 'tegra/cleanup' into next/soc
This is a dependency for the tegra/soc branch. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/tegra/clk-tegra20.c36
1 files changed, 2 insertions, 34 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 1e2de7305362..b92d48be4cc9 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -711,8 +711,8 @@ static void tegra20_pll_init(void)
}
static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
- "pll_p_cclk", "pll_p_out4_cclk",
- "pll_p_out3_cclk", "clk_d", "pll_x" };
+ "pll_p", "pll_p_out4",
+ "pll_p_out3", "clk_d", "pll_x" };
static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
"pll_p_out3", "pll_p_out2", "clk_d",
"clk_32k", "pll_m_out1" };
@@ -721,38 +721,6 @@ static void tegra20_super_clk_init(void)
{
struct clk *clk;
- /*
- * DIV_U71 dividers for CCLK, these dividers are used only
- * if parent clock is fixed rate.
- */
-
- /*
- * Clock input to cclk divided from pll_p using
- * U71 divider of cclk.
- */
- clk = tegra_clk_register_divider("pll_p_cclk", "pll_p",
- clk_base + SUPER_CCLK_DIVIDER, 0,
- TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
- clk_register_clkdev(clk, "pll_p_cclk", NULL);
-
- /*
- * Clock input to cclk divided from pll_p_out3 using
- * U71 divider of cclk.
- */
- clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3",
- clk_base + SUPER_CCLK_DIVIDER, 0,
- TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
- clk_register_clkdev(clk, "pll_p_out3_cclk", NULL);
-
- /*
- * Clock input to cclk divided from pll_p_out4 using
- * U71 divider of cclk.
- */
- clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4",
- clk_base + SUPER_CCLK_DIVIDER, 0,
- TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
- clk_register_clkdev(clk, "pll_p_out4_cclk", NULL);
-
/* CCLK */
clk = tegra_clk_register_super_mux("cclk", cclk_parents,
ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,