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author | Codrin Ciubotariu <codrin.ciubotariu@microchip.com> | 2022-03-04 21:26:16 +0300 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-04-08 15:23:47 +0300 |
commit | 7a778371f9f2d8c8d6301b4207188a0ef9d9eb16 (patch) | |
tree | 727400508b06a3ae6c206acb1f03089dc39724a7 /drivers/clk | |
parent | 4b8a71f206c94445317179b79d7f91996f40dcfc (diff) | |
download | linux-7a778371f9f2d8c8d6301b4207188a0ef9d9eb16.tar.xz |
clk: at91: sama7g5: fix parents of PDMCs' GCLK
[ Upstream commit 1a944729d8635fa59638f24e8727d5ccaa0c8c19 ]
Audio PLL can be used as parent by the GCLKs of PDMCs.
Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220304182616.1920392-1-codrin.ciubotariu@microchip.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/at91/sama7g5.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 019e712f90d6..9eed97a299d0 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -687,16 +687,16 @@ static const struct { { .n = "pdmc0_gclk", .id = 68, .r = { .max = 50000000 }, - .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, - .pp_mux_table = { 5, 8, }, + .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, + .pp_mux_table = { 5, 9, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "pdmc1_gclk", .id = 69, .r = { .max = 50000000, }, - .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, - .pp_mux_table = { 5, 8, }, + .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, + .pp_mux_table = { 5, 9, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, |