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authorSascha Hauer <s.hauer@pengutronix.de>2016-10-21 16:11:37 +0300
committerLinus Walleij <linus.walleij@linaro.org>2016-10-24 17:33:11 +0300
commit66a37c3bbf7348758a154fe99f8035df2874ebeb (patch)
tree184d70205c8dc47c7ceba855463fba29b54f985c /drivers/gpio
parent4035cc15b99f4f4a4e29081b82aca010137e33da (diff)
downloadlinux-66a37c3bbf7348758a154fe99f8035df2874ebeb.tar.xz
gpio: mxs: use enable/disable regs to (un)mask irqs
The mxs gpio controller does not only have a mask register to mask interrupts, but also enable/disable registers. Use the enable/disable registers rather than the mask register. This does not have any advantage for now, but makes the next patch simpler. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/gpio-mxs.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index b9daa0bf32a4..1cf579f670ec 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -211,12 +211,13 @@ static int __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
ct = gc->chip_types;
ct->chip.irq_ack = irq_gc_ack_set_bit;
- ct->chip.irq_mask = irq_gc_mask_clr_bit;
- ct->chip.irq_unmask = irq_gc_mask_set_bit;
+ ct->chip.irq_mask = irq_gc_mask_disable_reg;
+ ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
ct->chip.irq_set_type = mxs_gpio_set_irq_type;
ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
- ct->regs.mask = PINCTRL_IRQEN(port);
+ ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
+ ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
IRQ_NOREQUEST, 0);