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authorCharlene Liu <charlene.liu@amd.com>2018-08-27 18:31:08 +0300
committerAlex Deucher <alexander.deucher@amd.com>2018-09-14 23:46:52 +0300
commitd77f778e59ca858e1fb1e9d4946080d689c04711 (patch)
tree8de8f2e158d6c9b6e1c040aed4cffae19c8c584c /drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
parent0957dc7097a3f462f6cedb45cf9b9785cc29e5bb (diff)
downloadlinux-d77f778e59ca858e1fb1e9d4946080d689c04711.tar.xz
drm/amd/display: Fix 3D stereo issues.
We were not providing the correct pixel clocks to DML for marks calculation. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 32b34134c501..80ec09eef44f 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -852,8 +852,9 @@ bool dcn_validate_bandwidth(
v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
- v->vactive[input_idx]
- pipe->stream->timing.v_front_porch;
- v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f;
-
+ v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz/1000.0;
+ if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
+ v->pixel_clock[input_idx] *= 2;
if (!pipe->plane_state) {
v->dcc_enable[input_idx] = dcn_bw_yes;
v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;