diff options
| author | Vladimir Stempen <vladimir.stempen@amd.com> | 2021-02-24 22:02:32 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-02 22:07:59 +0300 |
| commit | 783bf4035cb7f2707ad760fbc06f6be01a553f0a (patch) | |
| tree | 227c008f5b0c41de8ebf935f90bc10219169f4c5 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | |
| parent | 640a28b50c4ad502b931750f13a5f743449e5755 (diff) | |
| download | linux-783bf4035cb7f2707ad760fbc06f6be01a553f0a.tar.xz | |
drm/amd/display: Fix 64 bit divisions on 32 bit platforms by using div64 API
[why]
Synchronization displays with different timings feature uses division
operator for 64 bit division, which is not supported by 32 bit platforms
[how]
Use div64 API for 64 bit division
Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com>
Tested-by: Bindu Ramamurthy<bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c index ef6ee03175e0..ea7eaf7d755f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c @@ -323,8 +323,8 @@ void optc2_align_vblanks( uint32_t master_v_active = 0; uint32_t master_h_total = 0; uint32_t slave_h_total = 0; - uint64_t L, XY, p = 10000; - uint32_t X, Y; + uint64_t L, XY; + uint32_t X, Y, p = 10000; uint32_t master_update_lock; /* disable slave OTG */ @@ -355,11 +355,12 @@ void optc2_align_vblanks( REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total); /* calculate when to enable slave OTG */ - L = p * slave_h_total * master_pixel_clock_100Hz / - master_h_total / slave_pixel_clock_100Hz; - XY = L / p; + L = (uint64_t)p * slave_h_total * master_pixel_clock_100Hz; + L = div_u64(L, master_h_total); + L = div_u64(L, slave_pixel_clock_100Hz); + XY = div_u64(L, p); Y = master_v_active - XY - 1; - X = ((XY + 1) * p - L) * master_h_total / master_clock_divider / p; + X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider); /* * set master OTG to unlock when V/H |