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| author | Matt Roper <matthew.d.roper@intel.com> | 2021-07-23 20:06:18 +0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-07-24 05:57:25 +0300 |
| commit | 3c73553f56cdbf2df5af574b3066e2bd7d16e2f7 (patch) | |
| tree | 5c8e1476a60a75ca49ea0b48975f6fb4e9adff47 /drivers/gpu/drm/i915/display/intel_display.c | |
| parent | 9b52aa720168859526bf90d77fa210fc0336f170 (diff) | |
| download | linux-3c73553f56cdbf2df5af574b3066e2bd7d16e2f7.tar.xz | |
drm/i915: Program chicken bit during DP MST sequence on TGL+
A new step has been added to the DP modeset sequences for all platforms
with display version 12 and beyond: if enabling DP MST with FEC, we
need to set a chicken bit before enabling the transcoder. The chicken
bit should be disabled again before disabling the transcoder (which we
can do unconditionally since it shouldn't be set anyway in non-MST
cases).
Bspec: 49190, 54128, 55424
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723170618.1477415-1-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 419784f7ef85..a4cdf7af7712 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1035,6 +1035,10 @@ void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) if (!IS_I830(dev_priv)) val &= ~PIPECONF_ENABLE; + if (DISPLAY_VER(dev_priv) >= 12) + intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), + FECSTALL_DIS_DPTSTREAM_DPTTG, 0); + intel_de_write(dev_priv, reg, val); if ((val & PIPECONF_ENABLE) == 0) intel_wait_for_pipe_off(old_crtc_state); |